Compaq AlphaServer ES45 Service Manual page 384

Table D–10 21274 Cchip Miscellaneous Register Fields
Name Bits
RES <63:44>
DEVSUP <43:40>
REV <39:32>
NXS <31:29>
NXM <28>
RES <27:25>
ACL <24>
ABT <23:20>
ABW <19:16>
IPREQ <15:12>
D-24 ES45 Service Guide
Initial
Type State Description
MBZ, RAZ 0 Reserved.
WO 0
RO 1 Cchip revision reads as 16
RO 0 NXM source—Device that caused
the NXM. Unpredictable if NXM
not set.
0 = CPU0
2 = CPU2
4 = P-chip 0
6, 7 = Reserved
R, W1C 0
Nonexistent memory address
detected. Sets DRIR<63> and locks
the NXS field until it is cleared.
MBZ, RW 0 Reserved.
WO 0
Arbitration clear—writing a 1 to
this bit clears the ABT and ABW
fields.
R, W1S 0
Arbitration try—writing a 1 to
these bits sets them.
R, W1S 0
Arbitration won—writing a 1 to
these bits sets them unless one is
already set, in which case the write
is ignored.
WO 0 Interprocessor interrupt request—
write a 1 to the bit corresponding
to the CPU you want to interrupt.
Writing a 1 here sets the
corresponding bit in the IPINTR.
1 = CPU1
3 = CPU3
5 = P-chip 1