Compaq AlphaServer ES45 Service Manual page 36

Memory Architecture
Memory throughput in this system is maximized by the following features:
•
Two independent, wide memory data buses
•
Very low memory latency (120 ns) and high bandwidth with 125 MHz clock
•
ECC memory
Each data bus is 256 bits wide (32 bytes). The memory bus speed is 125 MHz.
This yields 4 GB/sec bandwidth per bus (32 x 125 MHz = 4 GB/sec). The
maximum bandwidth is 8 GB/sec.
The switch interconnect design takes full advantage of the capabilities of the
two wide data buses. The 256 data bits are distributed equally over two
memory motherboards (MMBs). Simultaneously, in a read operation, 128 bits
come from one MMB and the other 128 bits come from another MMB, to make
one 256-bit read. Another 256-bit read operation can occur at the same time on
the other independent data bus.
In addition, two address buses per MMB (one for each array) allow overlapping/
pipelined accesses to maximize use of each data bus. When all arrays are
identical (same size), the memory is interleaved; that is, sequential blocks of
memory are distributed across all four arrays.
Memory Options
Each memory option consists of a set of four 125 MHz, 200-pin JEDEC-standard
DIMMs with PECL clocks. The DIMMs are synchronous DRAMs. Memory
options are available in the following sizes:
•
512 Mbytes (128 MB DIMMs)
•
1 Gbyte (256 MB DIMMs)
•
2 Gbytes (512 MB DIMMs)
•
4 Gbytes (1 GB DIMMs)
Memory options are installed into memory motherboards (MMBs) located on the
system motherboard (see Figure 1–8). There are four MMBs. The MMBs have
either four or eight slots for installing DIMMs. See Chapter 6 for memory
configuration.
1-18 ES45 Service Guide