1.10 Memory Architecture and Options
The system has two 256-bit wide memory data buses, which can move
large amounts of data simultaneously.
Figure 1–10 Memory Architecture
MMB3
MMB2
MMB1
MMB0
Address Arrays 0 & 2
Address Arrays 1 & 3
256 Data + 32 Check Bits
256 Data + 32 Check Bits
Data
Data
Bus 0
Bus 1
C-Chip
To all eight D-Chips
To all eight D-Chips
PK0272A
System Overview
1-17