Compaq AlphaServer ES45 Service Manual page 377

Table D–8 I_CTL Register Fields (Continued)
Name Extent
PCT0_EN <18>
SINGLE_ISSUE_H <17>
VA_FORM_32 <16>
VA_48 <15>
Type Description
RW,0 Enable performance counter #0. If this bit is
one, the performance counter will count if
EITHER the system (SPCE) or process
(PPCE) performance counter enable is set.
RW,0 When set, this bit forces instructions to
issue only from the bottom-most entries of
the IQ and FQ.
RW,0 This bit controls address formatting on a
read of the IVA_FORM register.
RW,0 This bit controls the format applied to
effective virtual addresses by the
IVA_FORM register and the Ibox virtual
address sign extension checkers. When
VA_48 is clear, 43-bit virtual address format
is used, and when VA_48 is set, 48-bit
virtual address format is used. The effect of
this bit on the IVA_FORM register is
identical to the effect of VA_CTL<VA_48>
on the VA_FORM register.
When VA_48 is set, the sign extension
checkers generate an ACV if va<63:0> ≠
SEXT(va<47:0>). When VA_48 is clear, the
sign extension checkers generate an ACV if
va<63:0> ≠ SEXT(va<42:0>).
This bit also affects DTB_DOUBLE Traps. If
set, the DTB double miss traps vector to the
DTB_DOUBLE_4 entry point.
DTB_DOUBLE PALcode flow selection is
not affected by VA_CTL<VA_48>.
Continued on next page
Registers D-17