D.7 Interrupt Summary Register (ISUM)
The Interrupt Summary Register (ISUM) is a read-only register that
records all pending hardware, software, and AST interrupt requests
that have their corresponding enable bit set.
If a new interrupt (hardware, serial line, crd, or performance counters) occurs
simultaneously with an ISUM read, the ISUM read returns zeros. That
condition is normally assumed to be a passive release condition. The interrupt is
signaled again when the PALcode returns to native mode. The effects of this
condition can be minimized by reading ISUM twice and ORing the results.
63
EI[5:0]
SL
CR
PC[1:0]
SI[15:1]
ASTU
ASTS
ASTE
ASTK
D-12
ES45 Service Guide
39
38
33
32
31
30
29
28
14
13
11 10
9
8
5
4
3
2
0
LK99-0024A