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Table D–14 Pchip Error Register (Continued)
Field
Bits
DCRTO
<3>
PERR
<2>
SERR
<1>
LOST
<0>
D-34
ES45 Service Guide
Type
Init
Description
R,W1C
0
Delayed completion Retry timeout as
PCI target.
R,W1C
0
Pchip received a p_err_l assertion on
data it sent to the PCI. If the command
logged in bits <55:52> of this register is
a read, the PCI transaction that
encountered the error was a DMA Read
or a PTP read on the source bus and the
Pchip was the target. If the command
logged is a write, the transaction that
encountered the error was a PIO Write
or a PTP write on the destination bus.
R,W1C
0
Set when serr_l assertion is detected on
the PCI. Does not log any other
information in this register. Does not
affect the logging of the Lost bit.
R,W1C
0
Lost an error because it was detected
after this register was locked.
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Troubleshooting
