Compaq AlphaServer ES45 Service Manual page 409

Table D–23 Bit Definition of Logout Frame Registers (Continued)
Register
Identification Bit Field
EXC_ADDR <0>
<63:2>
IER_CM
<4:3>
<13>
<28:14>
<30:29>
<31>
<32>
<38:33>
I_SUM <4:3>
<10:9>
<28:14>
<32>
<31>
<30:29>
<38:33>
PAL_BASE <43:15>
Text Translation Description
Set = exception or interrupt occurred in PAL mode
Contains the PC address of the instruction that would
have executed if the error interrupt did not occur.
00(Bin) = Kernel Mode, 01(Bin) = Executive Mode,
10(Bin) = Supervisor Mode, 11(Bin) = User Mode
Set = enables those AST interrupt requests by ASTER
Software interrupt enables
Performance counter interrupt enables
Set = Correctable read error interrupt enabled
Set = Serial Line Interrupt Enabled
External IRQ<5:0> enable
AST Kernel and Executive Interrupts pending ;
<3> Set = Kernel Mode AST interrupt pending,
<4> Set =Executive Mode AST interrupt pending
AST Supervisor and User Interrupts pending ;
<9> Set =Supervisor Mode AST interrupt pending,
<10> Set =User Mode AST interrupt pending
Software interrupts pending
Serial line interrupt pending
Set = Corrected read interrupt pending
Performance counter interrupts pending
External interrupts pending
Contains the physical base address for PALcode
Continued on next page
Registers D-49