Dcache Status Register Fields - Compaq AlphaServer ES45 Service Manual

D.3 Dcache Status Register (DC_STAT)
The Dcache Status Register (DC_STAT) is a read-write register. If a
Dcache tag parity error or data ECC error occurs, information about
the error is latched in this register.
63
SEO
ECC_ERR_LD
ECC_ERR_ST
TPERR_P1
TPERR_P0
Table D–3 Dcache Status Register Fields
Name Bits
Reserved <63:5>
SEO <4>
ECC_ERR_LD <3>
ECC_ERR_ST <2>
TPERR_P1 <1>
TPERR_P0 <0>
D-6 ES45 Service Guide
Type Description
Reserved for Compaq.
W1C
Second error occurred. When set, indicates that a
second D-cache store ECC error occurred within 6
cycles of the previous D-cache store ECC error.
W1C ECC error on load. When set, indicates that a
single-bit ECC error occurred while processing a
load from the D-cache or any fill.
W1C ECC error on store. When set, indicates that an
ECC error occurred while processing a store.
W1C Tag parity error—pipe 1. When set, indicates that
a D-cache tag probe from pipe 1 resulted in a tag
parity error. The error is uncorrectable and
results in a machine check.
W1C Tag parity error—pipe 0. When set, this bit
indicates that a D-cache tag probe from pipe 1
resulted in a tag parity error. The error is
uncorrectable and results in a machine check.
5 4 3 2 1 0
LK99-0042A