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D.2 Memory Management Status Register
(MM_STAT)
The Memory Management Status Register (MM_STAT) is a read-only
register. When a Dstream TB miss or fault occurs, information about
the error latched in MM_STAT.MM_STAT is not updated when a
LD_VPTE gets a DTB miss instruction.
63
DC_TAG_PERR
OPCODE[5:0]
FOW
FOR
ACV
WR
Table D–2 Memory Management Status Register Fields
Name
Bits
Reserved
<63:11>
<10>
DC_TAG_
PERR
OPCODE
<9:4>
FOW
<3>
FOR
<2>
ACV
<1>
WR
<0>
Type Description
Reserved for Compaq.
RO
This bit is set when a D-cache tag parity error occurs during
the initial tag probe of a load or store instruction. The error
created a synchronous fault to the D_FAULT PALcode entry
point and is correctable. The virtual address associated with
the error is available in the VA register.
RO
Opcode of the instruction that caused the error. HW_LD is
displayed as 3 and HW_ST is displayed as 7.
RO
Set when a fault-on-write error occurs during a write
transaction and PTE<FOW> was set.
RO
Set when a fault-on-read error occurs during a read
transaction and PTE<FOR> was set.
RO
Set when an access violation occurs during a transaction.
Access violations include a bad virtual address.
RO
Set when an error occurs during a write transaction.
11
10
9
4 3 2
1
0
LK99-0039A
Registers
D-5
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