Appendix D
Registers
D.1
D.2
D.3
Dcache Status Register (DC_STAT)..................................................... D-6
D.4
Cbox Read Register .............................................................................. D-7
D.5
D.6
Interrupt Enable and Current Processor Mode Register (IER_CM).. D-10
D.7
D.8
D.9
Ibox Control Register (I_CTL)............................................................ D-15
D.10
D.11
D.12
D.13
D.14
D.15
D.16
D.17
D.18
D.19
D.20
D.21
D.22
D.23
D.24
E.1
E.2
E.3
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