Compaq AlphaServer ES45 Service Manual page 21

This system is designed to fully exploit the potential of the Alpha EV68 CB chip
by using a switch-based (or point-to-point) interconnect system. With a
traditional bus design, the processors, memory, and I/O modules share the bus.
As the number of bus users increases, the transactions interfere with one
another, increasing latency and decreasing aggregate bandwidth. With a
switch-based system, speed is maintained and little degradation in performance
occurs as the number of CPUs, memory, and I/O users increases.
The switched system interconnect uses a set of complex microprocessor support
chips that route the traffic over multiple paths. This chipset consists of one C-
chip, two P-chips, and eight D-chips.
•
C-chip. Provides the command interface from the CPUs and main memory.
The C-chip allows each CPU to do transactions simultaneously.
•
D-chips. Provide the data path for the CPUs, main memory, and I/O.
•
P-chips. Provide the interface to the I/O with two buses per chip.
The chipset supports up to four CPUs and up to 32 Gbytes of memory.
Interleaving occurs when at least two sibling or nonsibling memory arrays are
used.
Two 256-bit memory buses support four memory arrays, yielding a maximum
8 Gbytes/sec system bandwidth. Transactions are ECC protected. Upon the
receipt of data, the receiver checks for data integrity and corrects any errors.
System Overview 1-3