Compaq AlphaServer ES45 Service Manual page 411

Table D–23 Bit Definition of Logout Frame Registers (Continued)
ID Bit Field Text Translation Description
MISC
<43:40> Suppress IRQ1 interrupts to 1(Hex) for CPU0, 2(Hex) for CPU1,
4(Hex) for CPU2, and 8(Hex) for CPU3 Cchip
<39:32> Cchip Revision Level : 00-07(Hex) for C2, 08-0F(Hex) for C4
<31:29> 0(Hex) for CPU0, 1(Hex) for CPU1, 2(Hex) for CPU2, 3(Hex) for
CPU3, 4(Hex) for Pchip0, 5(Hex) for Pchip1, as device (source) which
caused the NXM
<28> Set = NXM address detected, <31:29> are locked, DRIR <63> is set
<24> Write 1 = Arbitration Clear
<23:20> =1(Hex) for CPU0, 2(Hex) for CPU1, 4(Hex) for CPU2, and 8(Hex)
for CPU3 Arbitration Trying
<19:16> =1(Hex) for CPU0, 2(Hex) for CPU1, 4(Hex) for CPU2, and 8(Hex)
for CPU3 Arbitration Won
<15:12> =1(Hex) for CPU0, 2(Hex) for CPU1, 4(Hex) for CPU2, and 8(Hex)
for CPU3 to set interprocessor interrupt request.
<11:8> =1(Hex) for CPU0, 2(Hex) for CPU1, 4(Hex) for CPU2, and 8(Hex)
for CPU3 interprocessor interrupt (IRQ<3>) pending
<7:4> =1(Hex) for CPU0, 2(Hex) for CPU1, 4(Hex) for CPU2, and 8(Hex)
for CPU3 interval timer interrupt (IRQ<2>) pending
<1:0> =00(Bin) for CPU0, 01(Bin) for CPU1, 10(Bin) for CPU2, 11(Bin) for
CPU3 ID performing the read.
Continued on next page
Registers D-51