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Appendix D
Registers
This appendix describes 21264 (EV68) internal processor registers; 21274
(Titan) system support chipset registers; and dual-port RAM (DPR) registers
that are related to general logout frame errors. It also provides CPU and system
uncorrectable and correctable machine logout frames and error state bit
definitions of all the platform logout frame registers.
21264 (EV68) Registers
Ibox Status Register (I_STAT)
Memory Management Status Register (MM_STAT)
Dcache Status Register (DC_STAT)
Cbox Read Register
Exception Address Register (EXC_ADDR)
Interrupt Enable and Current Processor Mode Register (IER_CM)
Interrupt Summary Register (ISUM)
PAL Base Register (PAL_BASE)
Ibox Control Register (I_CTL)
Process Context Register (PCTX)
21274 (Titan) System Registers
21274 Cchip Miscellaneous Register (MISC)
21274 Device Interrupt Request Register (DIRn, n=0,1,2,3)
21274 Pchip Error Register (PERROR)
21274 Pchip System Error Register (SERROR)
21274 Array Address Registers
DPR Registers
DPR Registers (for 680 correctable error state capture)
2
DPR Registers (for I
C bus)
2
DPR Registers (power supply status from I
C bus)
DPR 680 Fatal Registers (for 680 uncorrectable error state capture)
Registers
D-1
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