Table of Contents
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PRIGRP[15:8]
PPRI[16]
PCISPD66[17]
CNGSTLT[21:18]
PTPDESTEN[29:22]
DPCEN[30]
APCEN[31]
DCR_Timer[33:32]
EN_Stepping[34]
P0_APCTL
FBTB[0]
THDIS[1]
CHAINDIS[2]
TGLAT[4:3]
HOLE_Enable[5]
MWIN_Enable[6]
ARBENA[7]
PRIGRP[15:8]
PCISPD66[17]
CNGSTLT[21:18]
PTPDESTEN[29:22]
DPCEN[30]
APCEN[31]
DCR_Timer[33:32]
EN_Stepping[34]
AGP_Rate[53:52]
AGP_SBA_Enabled[54]
AGP_Enabled[55]
AGP_Present[57]
AGP_HP_RD[60:58]
AGP_LP_RD[63:61]
P1_SCTL
REV[7:0]
PID[8]
RPP[9]
ECCEN[10]
SWARB[12:11]
CRQMAX[19:16]
CDQMAX[23:20]
PTPMAX[27:24]
INUM[28]
5-14
ES45 Service Guide
x65
x0
x1
xC
x81
x0
x0
x1
x1
x3320 6C65 646F 4D20 Pchip0 Aport Control
x0
x0
x0
x0
x1
x0
x0
x4D
x1
xB
x91
x1
x0
x1
x1
x2
x0
x0
x1
x4
x1
x3A54 4556 2D51 0046 Pchip1 System Control
x46
x0
x0
x0
x0
x1
x5
xD
x0
GPCI Frequency = 66 MHz
12 DMA Reads Retry w/no
delayed Completion
Data Parity Checking
Disabled
Address Parity Checking
Disabled
DCR Timer Count = 2^11
Address Stepping Enabled
Register
TGLAT = 128 PCI Clocks
Window-Hole Enabled
APCI = 66MHz
11 DMA Reads Retry w/no
delayed Completion
Address Parity Error
Checking Disabled
DCRT Count = 2^11
PCI Config Address Stepping
Enabled
AGP Rate = 4X
AGP Bus Enabled
4 Cchip HP Outstanding
Reads
1 Cchip LP Outstanding Read
Register
Pchip PID = 0
Pchip1 ECC Disabled
GPCI > APCI > AGPX
Max Cchip Requests from
both Pchips
Max Dchip Data Xfrs from
both Pchips
Max PTP Reqs from both
Pchips
256K MAX PTP/PIO Writes
Enabled to bypass PIO Read
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Table of Contents
Troubleshooting
