Table of Contents
Advertisement
Table D–9 PCTX Register Fields
Name
Reserved
ASN<7:0>
Reserved
ASTRR<3:0>
ASTER<3:0>
Reserved
Extent
Type
Description
<63:47>
<46:39>
RW
Address space number.
<38:13>
<12:9>
RW
AST request register—used to request AST
interrupts in each of the four processor
modes.
To generate a particular AST interrupt, its
corresponding bits in ASTRR and ASTER
must be set, along with the ASTE bit in
IER.
Further, the value of the current mode bits
in the PS register must be equal to or
higher than the value of the mode associ-
ated with the AST request.
The bit order with this field is:
User Mode
Supervior Mode
Executive Mode
Kernel Mode
<8:5>
RW
AST enable register—used to individually
enable each of the four AST interrupt
requests.
The bit order with this field is:
User Mode
Supervisor Mode
Executive Mode
Kernel Mode
<4:3>
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
Continued on next page
Registers
D-21
Advertisement
Table of Contents
Troubleshooting
