Brocade Communications Systems A7990A - StorageWorks SAN Director 4/16 Blade Switch Command Reference Manual page 87

Brocade fabric os command reference manual (53-1000240-01, november 2006)
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Note: Enter commands in lowercase only; mixed case is for readability.
2.
Set up the hardware such that each ASIC is read by all of the ports in the switch. Data received is
compared against the frame written into the ASIC.
3.
Repeat step 1 and step 2 the for the complemented pattern.
4.
Repeat this procedure for each ASIC pair in the blade under test.
The pattern used is generated similarly as in data read/write subtest except that only 2112 bytes are
generated.
Parity Error Subtest
The forced bad parity error subtest verifies that a bad parity can be detected, its error flag set, and
interrupt bits set.
The test method is as follows:
1.
Clear the error and interrupt bits of all ASICs.
2.
Write 64 bytes with bad parity to all ASICs at offset 0.
3.
Read each of the ASIC pairs at offset 0 and check that the error and interrupt bits are set.
4.
Repeat steps 1 through 3 for offset 1 through 10.
Buffer Number Error Subtest
The forced bad buffer number error subtest verifies that the bad buffer number in the data packet can be
detected and its error flag and interrupt bits set.
The test method is as follows:
1.
Clear the error and interrupt bits of all ASICs.
2.
Set up the hardware so that transmission of data includes a bad buffer.
3.
For each of the 11 possible offsets for each ASIC X in the switch:
a.
b.
c.
Fabric OS Command Reference Manual
Publication Number: 53-1000240-01
Port 0 reads the central memory in ASIC 0.
Port 1 reads the central memory in ASIC 0.
Port 14 reads the central memory in ASIC 0.
Port 15 reads the central memory in ASIC 0.
Port 0 reads the central memory in ASIC 1.
Port 1 reads the central memory in ASIC 1.
Port 14 reads the central memory in ASIC 1.
Port 15 reads the central memory in ASIC 1.
Port 15 reads the central memory in ASIC 2.
Port 15 reads the central memory in ASIC 3.
Write a 64-byte pattern in the central memory.
Read X from all ASIC Y in the switch.
For ASIC X, ensure:
centralMemoryTest
2
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