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5.5
Bus Access
5.5.1
Number of clocks for access
The following table shows the number of basic clocks required for accessing each resource.
Area (Bus Width)
Bus Cycle Type
Instruction fetch (normal access)
Instruction fetch (branch)
Operand data access
Note 2 + n clocks (n: Number of wait states) when the separate bus mode is selected.
Remark
Unit: Clocks/access
5.5.2
Bus size setting function
The bus size of each external memory area selected by CSn can be set (to 8 bits or 16 bits) by using the BSC
register.
The external memory area of the V850ES/SA2 (0100000H to 0BFFFFFH) is selected by CS0 to CS3.
The external memory area of the V850ES/SA3 (0100000H to 0FFFFFFH) is selected by CS0 to CS3.
(1) Bus size configuration register (BSC)
This register can be read or written in 16-bit units.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not
access an external memory area other than the one for this initialization routine until the
initial settings of the BSC register are complete. However, external memory areas whose
initial settings are complete may be accessed.
After reset:
BSC
CSn signal
BSn0
Caution Be sure to set bits 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0.
CHAPTER 5 BUS CONTROL FUNCTION
Internal ROM (32 bits)
1
2
3
5555H
R/W
Address:
15
14
13
0
1
0
7
6
5
0
BS30
0
CS3
Data bus width of CSn space (n = 0 to 3)
0
8 bits
1
16 bits
Preliminary User's Manual U15905EJ1V0UD
Internal RAM (32 bits)
1 or 2
1 or 2
1
FFFFF066H
12
11
10
1
0
1
4
3
2
BS20
0
BS10
CS2
CS1
External Memory (16 bits)
Note
3 + n
Note
3 + n
Note
3 + n
9
8
0
1
1
0
0
BS00
CS0
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