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4.8 Bus Hold Function
4.8.1 Function outline
If pins PCM2 and PCM3 are specified in the control mode, the HLDAK and HLDRQ functions become valid.
If it is determined that the HLDRQ pin has become active (low level) as a bus mastership request from another bus
master, the external address/data bus and each strobe pin are shifted to high impedance and then released (bus hold
state). If the HLDRQ pin becomes inactive (high level) and the bus mastership request is canceled, driving of these
pins begins again.
During the bus hold period, the internal operations of the V850E/IA1 continue until the external memory or on-chip
peripheral I/O register is accessed.
The bus hold state can be known by the HLDAK pin becoming active (low level). The period from when the
HLDRQ pin becomes active (low level) to when the HLDAK pin becomes active (low level) is at least 2 clocks.
In a multiprocessor configuration, etc., a system with multiple bus masters can be configured.
4.8.2 Bus hold procedure
The procedure of the bus hold function is illustrated below.
<1> HLDRQ = 0 accepted
<2> All bus cycle start requests held pending
<3> End of current bus cycle
<4> Transition to bus idle state
<5> HLDAK = 0
<6> HLDRQ = 1 accepted
<7> HLDAK = 1
<8> Releases pending bus cycle start request
<9> Start of bus cycle
HLDRQ (input)
HLDAK (output)
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CHAPTER 4 BUS CONTROL FUNCTION
Normal state
Bus hold state
Normal state
<1> <2>
<3><4> <5>
User's Manual U14492EJ3V0UD
<6> <7><8><9>
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