Bus Hold Function; Functional Outline - NEC V850E/RS1 User Manual

5.7 Bus Hold Function

5.7.1 Functional outline

The HLDAK and HLDRQ functions are valid if the PCM2 and PCM3 pins are set in the control mode.
When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus
mastership, the external address/data bus goes into a high-impedance state and is released (bus hold
status). If the request for the bus mastership is cleared and the HLDRQ pin is deasserted (high level),
driving these pins is started again.
During the bus hold period, execution of the program in the internal ROM and internal RAM is continued
until a peripheral I/O register or the external memory is accessed.
The bus hold status is indicated by assertion of the HLDAK pin (low level). The bus hold function
enables the configuration multi-processor type systems in which two or more bus masters exist.
Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus
sizing function or a bit manipulation instruction.
CPU bus lock
Read-modify-write access of
bit manipulation instruction
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Chapter 5 Bus Control Function
Data Bus
Status
Width
Word access to even address
16 bits Word access to odd address
Halfword access to odd address Between first and second access
Word access
8 bits
Halfword access
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User's Manual U16702EE3V2UD00
Timing in Which Bus Hold Request
Access Type
Between first and second access
Between first and second access
Between second and third access
Between first and second access
Between second and third access
Between third and fourth access
Between first and second access
Between read access and write
_
access
Is Not Acknowledged
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