Bcache Port Pins; Range Of Maximum Bcache Clock Ratios - Compaq 21264 Hardware Reference Manual

The Bcache supports the following multiples of the GCLK period: 1.5X (dual-data
mode only), 2X, 2.5X, 3X, 3.5X, 4X, 5X, 6X, 7X, and 8X. However, the 21264/EV67
imposes a maximum Bcache clock period based on the SYSCLK ratio. Table 4–35 lists
the range of maximum Bcache clock periods. Section 4.7.8.2 describes fast mode.
Table 4–35 Range of Maximum Bcache Clock Ratios
Bcache Clock Ratio with Fast Mode
SYSCLK Ratio Enabled
1.5X 4.0X
2.0X 4.0X
2.5X 5.0X
3.0X 6.0X
3.5X 7.0X
4.0X 7.0X
5.0X 8.0X
6.0X 8.0X
7.0X 8.0X
8.0X 8.0X
The 21264/EV67 provides a range of programmable Cbox CSRs to manipulate the
Bcache port pins so that a variety of industry-standard SSRAMs can communicate effi-
ciently with the 21264/EV67. The following SSRAMs can be used:.
•
Nonburst mode Reg/Reg late-write SSRAMs
•
Burst mode Reg/Reg late-write dual-data SSRAMs

4.8.1 Bcache Port Pins

Table 3–1 defines the 21264/EV67 signal types referred to in this section. Table 4–36
lists the Bcache port pin groups along with their type, number, reference clock, and
functional description.
Table 4–36 Bcache Port Pins
Pin Name
BcAdd_H[23:4]
BcCheck_H[15:0]
BcData_H[127:0]
BcDataInClk_H[7:0]
BcDataOE_L
BcDataOutClk_H[3:0]
BcDataOutClk_L[3:0]
Alpha 21264/EV67 Hardware Reference Manual
Type Count Reference Clock
O_PP 20 Int_Index_BcClk
B_DA_PP 16 Int_Data_BcClk
BcDataInClk_H
B_DA_PP 128 Int_Data_BcClk
BcDataInClk_H
I_DA 8 NA
O_PP 1 Int_Index_BcClk
O_PP 8 NA
Bcache Clock Ratio with Fast Mode
Disabled
7.0X
7.0X
8.0X
8.0X
8.0X
8.0X
8.0X
8.0X
8.0X
8.0X
Description
Bcache index
output ECC check bits for BcData
input
output Bcache data
input
Bcache data input clocks
Bcache data output enable/chip
select
Bcache data clocks— high and low
version
Cache and External Interfaces
Bcache Port
4–43