Cbox Write_Once Chain Order - Compaq 21264 Hardware Reference Manual

Cbox CSRs and IPRs
•
Only a brief description of each CSR is given. The functional description of these
CSRs is contained in Chapter 4.
•
The order of multibit vectors is [MSB:LSB], so the LSB is first bit in the Cbox
chain.
Table 5–24 describes the Cbox WRITE_ONCE chain order from LSB to MSB.
Table 5–24 Cbox WRITE_ONCE Chain Order
Cbox WRITE_ONCE Chain
32_BYTE_IO[0]
SKEWED_FILL_MODE[0]
SKEWED_FILL_MODE[0]
DCVIC_THRESHOLD[7:0]
BC_CLEAN_VICTIM[0]
SYS_BUS_SIZE[1:0]
SYS_BUS_FORMAT[0]
SYS_CLK_RATIO[4:1]
DUP_TAG_ENABLE[0]
PRB_TAG_ONLY[0]
FAST_MODE_DISABLE[0]
BC_RDVICTIM[0]
BC_CLEAN_VICTIM[0]
RDVIC_ACK_INHIBIT
SYSBUS_MB_ENABLE
SYSBUS_ACK_LIMIT[0:4]
SYSBUS_VIC_LIMIT[0:2]
BC_CLEAN_VICTIM[0]
BC_WR_WR_BUBBLE[0]
BC_RD_WR_BUBBLES[0:5]
BC_RD_RD_BUBBLE[0]
BC_SJ_BANK_ENABLE
BC_WR_RD_BUBBLES[0:3]
Internal Processor Registers
5–34
Description
Enable 32_BYTE I/O mode.
Asserted when Bcache is at 1.5X ratio.
Duplicate of prior bit.
Threshold of the number of Dcache victims that will accumulate
before streamed write transactions to the Bcache are initiated. The
Cbox can accumulate up to six victims for streamed Dcache pro-
cessing. This register is programmed with the decoded value of the
threshold count.
Enable clean victims to the system interface.
Size of SysAddOut and SysAddOut buses.
Indicates system bus format.
Speed of system bus.
Code Multiplier
0001 1.5X
0010 2.0X
0100 2.5X
1000 3.0X
Enable duplicate tag mode in the 21264/EV67.
Enable probe-tag only mode in the 21264/EV67.
When asserted, disables fast data movement mode.
Enables RdVictim mode on the pins.
Duplicate CSR.
Enable inhibition of incrementing acknowledge counter for RdVic
commands.
Enable MB commands offchip.
Sysbus acknowledge limit CSR.
Limit for victims.
Duplicate CSR.
Write to write GCLK bubble.
Read to write GCLK bubbles for the Bcache interface.
Read to read GCLK bubble for banked Bcaches.
Enable bank mode for Bcache.
Write to read GCLK bubbles.
Alpha 21264/EV67 Hardware Reference Manual