Compaq 21264 Hardware Reference Manual page 346

BC_SJ_BANK_ENABLE Cbox CSR
,
defined 5–34
BC_TAG_DDM_FALL_EN Cbox CSR
,
defined 5–35
BC_TAG_DDM_RISE_EN Cbox CSR
,
defined 5–36
BC_WR_RD_BUBBLES Cbox CSR
,
defined 5–34
BC_WR_WR_BUBBLE Cbox CSR
,
defined 5–34
BC_WRT_STS Cbox CSR
Bcache
,
banking 4–54
bubbles on the data bus
,
clocking 4–44
,
control pins 4–52
data read transactions
data single-bit correctable ECC error
data single-bit correctable ECC error on a probe
8–8
data write transactions
error case summary for
,
filling Dcache error
,
filling Icache error 8–5
forwarding clock pin groupings
,
maximum clock ratio
,
port 4–42
,
port pins 4–43
programming the size of
,
setting clock period
,
structure of 4–7
,
tag parity errors 8–5
,
tag read transactions
victim read during an ECB instruction error
8–7
victim read during Dcache/Bcache miss error
8–6
,
victim read error 8–6
,
BcAdd_H signal pins 3–3
,
characteristics 4–51
,
BcCheck_H signal pins 3–3
,
BcData_H signal pins 3–3
BcDataInClk_H signal pins
,
using 4–53
,
BcDataOE_L signal pin
BcDataOutClk_x signal pins
,
BcDataWr_L signal pin
,
BcLoad_L signal pin 3–4
,
BcTag_H signal pins 3–4
,
BcTagDirty_H signal pin
,
BcTagInClk_H signal pin
,
using 4–53
,
BcTagOE_L signal pin 3–4
BcTagOutClk_x signal pins
Index–2
,
4–47
,
4–47
,
4–49
,
4–54
, ,
5–39 7–13
,
4–49
,
4–47
,
8–5
,
4–48
,
8–10
8–6
,
E–1
4–42
,
4–51
4–45
4–47
,
,
,
4–43
,
4–43
,
4–43
, ,
3–3 4–43
,
3–3 4–43
, ,
3–4 4–43
,
3–4 4–44
,
4–44
,
4–44
,
3–4 4–44
,
3–4 4–44
,
4–44
, ,
3–4 4–44
BcTagParity_H signal pin
BcTagShared_H signal pin
BcTagValid_H signal pin
BcTagWr_L signal pin
BcVref signal pin
Bidirectional differential amplifier receiver -
open-drain. See B_DA_OD
Bidirectional differential amplifier receiver -
push-pull. See B_DA_PP
Binary multiple abbreviations
BiST. See Built-in self-test
Bit notation conventions
Bounder-scan register
Branch history table, initialized by BiST
Branch mispredication, pipeline abort delay from
,
2–16
,
Branch predictor
BSDL description of the boundary-scan register
B–1
,
Built-in self-test
,
load 7–6
C
C_ADDR Cbox read register field
C_DATA Cbox data register
at power-on reset state
C_SHFT Cbox shift register
at power-on reset state
C_STAT Cbox read register field
C_STS Cbox read register field
C_SYNDROME_0 Cbox read register field
C_SYNDROME_1 Cbox read register field
Cache block states
response to 21264/EV67 commands
,
transitions 4–10
,
Cache coherency
CALL_PAL entry points
Caution convention
Alpha 21264/EV67 Hardware Reference Manual
, ,
3–4 4–44
, ,
3–4 4–44
, ,
3–4 4–44
, ,
3–4 4–44
, ,
3–4 4–44
,
xix
,
xx
,
B–1
,
7–12
2–3
11–5
,
5–41
,
5–33
,
7–16
,
5–33
,
7–16
,
5–41
,
5–41
,
,
,
4–9
,
4–10
4–8
,
6–12
,
xx
,
,
5–41
5–41