Compaq 21264 Hardware Reference Manual page 350

I_CTL Ibox control register
,
after fault reset 7–8
,
after warm reset 7–11
at power-on reset state
,
PALshadow registers
,
through sleep mode
,
VA_48 field update
, ,
I_DA pin type 3–3 9–2
,
values for 9–3
,
I_DA_CLK pin type 3–3
,
values for 9–3
,
I_DC_POWER pin type
,
I_DC_REF pin type 3–3
,
values for 9–3
I_STAT Ibox status register
at power-on reset state
,
IACV fault 6–13
Ibox
,
branch predictor 2–3
clear virtual-to-physical map register
,
CLR_MAP
exception address register EXC_ADDR
exception and interrupt logic
exception summary register EXC_SUM
floating-point issue queue
hardware interrupt clear register HW_INT_CLR
5–12
Ibox control register I_CTL
Ibox process context register PCTX
Ibox status register I_STAT
Icache flush ASM register IC_FLUSH_ASM
5–21
Icache flush register IC_FLUSH
instruction fetch logic
instruction virtual address format register
IVA_FORM
instruction-stream translation buffer
,
integer issue queue 2–6
internal processor registers
interrupt enable and current processor mode
register IER_CM
interrupt summary register ISUM
ITB invalidate single register ITB_IS
ITB invalidate-all ASM (ASM=0) register
,
ITB_IAP 5–7
ITB invalidate-all register ITB_IA
ITB PTE array write register ITB_PTE
ITB tag array write register ITB_TAG
PAL base register PAL_BASE
performance counter control register
,
PCTR_CTL
ProfileMe register PMPC
,
register rename maps
,
retire logic 2–8
retire logic and mapper, required sequence for
D–1
sleep mode register SLEEP
software interrupt request register SIRR
,
subsections in 2–2
virtual program counter logic
Index–6
,
5–15
,
7–15
6–11
7–10
D–17
,
9–2
9–2
,
9–2
,
5–18
,
7–15
5–21
,
5–8
,
2–8
,
5–13
,
2–7
,
5–15
,
5–21
,
5–18
,
,
5–21
,
2–6
,
5–9
,
2–5
,
5–1
,
5–9
,
5–11
,
5–7
,
5–7
,
5–6
,
5–6
,
5–15
5–23
,
5–8
2–6
,
,
5–21
,
5–10
,
2–2
IC_FLUSH Icache flush register
at power-on reset state
IC_FLUSH_ASM Icache flush ASM register
Icache
,
data errors 8–2
error case summary for
fill from Bcache error
fill from memory error
flush register IC_FLUSH
initialized by BiST
tag, initialized by BiST
IEEE 1149.1
notes for compliance to
test port reset
test port, operation of
IEEE floating-point conformance
IEEE floating-point instruction opcodes
IER_CM interrupt enable and current processor mode
,
register
at power-on reset state
IMPLVER instruction values
Independent floating-point function codes
INIT_MODE Cbox CSR
Initialization mode processing
,
Input dc reference pin. See I_DC_REF pin type
Input differential amplifier clock receiver. See
I_DA_CLK pin type
Input differential amplifier receiver. See I_DA pin
type
Instruction fetch logic
Instruction fetch, issue, and retire unit. See Ibox
Instruction fetch, pipelined
Instruction issue rules
Instruction latencies, pipelined
Instruction ordering
Instruction retire latencies, minimum
Instruction retire rules
,
F31 2–22
floating-point divide
floating-point square root
,
pipelined 2–21
,
R31 2–22
Instruction slot, pipelined
Instruction-stream translation buffer
Int_Add_BcClk internal forwarded clock
4–48
Int_Data_BcClk internal forwarded clock
4–49
INT_FWD_CLK clock queue
Integer arithmetic trap, pipeline abort delay with
Alpha 21264/EV67 Hardware Reference Manual
,
7–15
,
8–9
,
8–5
,
8–7
,
5–21
,
7–12
,
7–12
,
11–7
,
7–16
,
11–3
,
A–14
,
A–9
5–9
,
7–15
,
2–38
,
, ,
5–39 7–12
,
7–12
,
2–6
,
2–14
,
2–16
,
2–20
,
2–30
,
2–21
,
2–22
,
2–22
,
2–14
,
2–5
,
4–44
,
4–44
,
4–30
,
5–21
A–11
,
,
,