Programming The System Interface Clocks; Programming Values For System Interface Clocks; Program Values For Data-Sample/Drive Csrs - Compaq 21264 Hardware Reference Manual

System Port

4.7.2 Programming the System Interface Clocks

The system forwarded clocks are free running and derived from the 21264/EV67
GCLK. The period of the system forwarded clocks is controlled by three Cbox CSRs,
based on the bit-rate ratio (similar to the Bcache bit-rate ratio) except that all transfers
are dual-data.
•
SYS_CLK_LD_VECTOR[15:0]
•
SYS_BPHASE_LD_VECTOR[3:0]
•
SYS_FDBK_EN[7:0]
Table 4–7 lists the programming values used to program the system interface clocks.
Table 4–7 Programming Values for System Interface Clocks
System Transfer SYS_CLK_LD_VECTOR
1.5X-DD 9249
2.0X-DD 3333
2.5X-DD 8C63
3.0X-DD 71C7
3.5X-DD C387
4.0X-DD 0F0F
5.0X-DD 7C1F
6.0X-DD F03F
7.0X-DD C07F
8.0X-DD 00FF
1
These are hexadecimal values.
In addition to programming of the clock CSRs, the data-sample/drive Cbox CSRs at the
pads have to be set appropriately. Table 4–8 shows the programmed values for these
system CSRs. In Table 4–8, each system forwarded clock is the inversion of the low-
assertion signal at the corresponding pin.
Table 4–8 Program Values for Data-Sample/Drive CSRs
CBOX CSR
SYS_DDM_FALL_EN[0]
SYS_DDM_RISE_EN[0]
SYS_DDM_RD_FALL_EN[0]
Cache and External Interfaces
4–18
1
SYS_BPHASE_LD_VECTOR
5
0
5
0
A
0
0
0
0
0
Description
Enables the update of 21264/EV67 system outputs based on the falling edge
of the system forwarded clock. (Always asserted)
Enables the update of 21264/EV67 system outputs based on the rising edge
of the system forwarded clock. (Always asserted)
Enables the sampling of incoming data on the falling edge of the incoming
forwarded clock. (Always asserted)
Alpha 21264/EV67 Hardware Reference Manual
1 1
SYS_FDBK_EN
02
01
02
10
04
01
40
10
04
01