Compaq 21264 Hardware Reference Manual page 301

Restriction 1 : Reset Sequence Required by Retire Logic and Mapper
addq r31,r31,r27
addt f31,f31,f26
mult f31,f31,f27
addq r31,r31,r28
addq r31,r31,r29
addt f31,f31,f28
mult f31,f31,f29
addq r31,r31,r30
addt f31,f31,f30
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
addq r31,r31,r0
/* stop deleting*/
mtpr r31,EV6__ITB_IA
mtpr r31,EV6__DTB_IA
mtpr r31,EV6__VA_CTL
mtpr r31,EV6__M_CTL
/*
** Create a stall outside the IQ until the mtpr EV6__ITB_IA retires.
** We can use DTB_ASNx even though we don't seem to follow the restriction on
** scoreboard bits (4-7).It's okay because there are no real dstream
** operations happening.
*/
mtpr r31,EV6__DTB_ASN0
mtpr r31,EV6__DTB_ASN1
mtpr r31,EV6__CC_CTL
mtpr r31,EV6__DTB_ALT_MODE/* clear DTB_ALT_MODE (SCRBRD=6)*/
/*
** MAP_SHADOW_REGISTERS
**
** The shadow registers are mapped. This code may be done by the SROM
Alpha 21264/EV67 Hardware Reference Manual
/* initialize Int. Reg. 27*/
/* initialize F.P. Reg. 26*/
/* initialize F.P. Reg. 27*/
/* initialize Int. Reg. 28*/
/* initialize Int. Reg. 29*/
/* initialize F.P. Reg. 28*/
/* initialize F.P. Reg. 29*/
/* initialize Int. Reg. 30*/
/* initialize F.P. Reg. 30*/
/* initialize retirator 63*/
/* initialize retirator 64*/
/* initialize retirator 65*/
/* initialize retirator 66*/
/* initialize retirator 67*/
/* initialize retirator 68*/
/* initialize retirator 69*/
/* initialize retirator 70*/
/* initialize retirator 71*/
/* initialize retirator 72*/
/* initialize retirator 73*/
/* initialize retirator 74*/
/* initialize retirator 75*/
/* initialize retirator 76*/
/* initialize retirator 77*/
/* initialize retirator 78*/
/* initialize retirator 79*/
/* initialize retirator 80*/
/* flush the ITB (SCRBRD=4) *** this also
turns on mapper source enables ****/
/* flush the DTB (SCRBRD=7)*/
/* clear VA_CTL (SCRBRD=5)*/
/* clear M_CTL (SCRBRD=6)*/
/* clear DTB_ASN0 (SCRBRD=4) creates a map-
stall under the above mtpr to SCRBRD=4*/
/* clear DTB_ASN1 (SCRBRD=7)*/
/* clear CC_CTL (SCRBRD=5)*/
PALcode Restrictions and Guidelines
D–3