Compaq 21264 Hardware Reference Manual page 144

Table 5–1 Internal Processor Registers (Continued)
Register Name
Instruction VA format
Current mode
Interrupt enable
Interrupt enable and current mode
Software interrupt request
Interrupt summary
Hardware interrupt clear
Exception summary
PAL base address
Ibox control
Ibox status
Icache flush
Icache flush ASM
Clear virtual-to-physical map
Sleep mode
Process context register
Process context register
Performance counter control
Mbox IPRs
DTB tag array write 0
DTB tag array write 1
DTB PTE array write 0
DTB PTE array write 1
DTB alternate processor mode
DTB invalidate all process (ASM = 0) DTB_IAP
DTB invalidate all
DTB invalidate single (array 0)
DTB invalidate single (array 1)
DTB address space number 0
DTB address space number 1
Memory management status
Mbox control
Dcache control
Dcache status
Internal Processor Registers
5–2
Index
Mnemonic (Binary)
IVA_FORM 0000 0111
CM 0000 1001
IER 0000 1010
IER_CM 0000 10xx
SIRR 0000 1100
ISUM 0000 1101
HW_INT_CLR 0000 1110
EXC_SUM 0000 1111
PAL_BASE 0001 0000
I_CTL 0001 0001
I_STAT 0001 0110
IC_FLUSH 0001 0011
IC_FLUSH_ASM 0001 0010
CLR_MAP 0001 0101
SLEEP 0001 0111
PCTX 01xn nnnn
PCTX 01xx xxxx
PCTR_CTL 0001 0100
DTB_TAG0 0010 0000
DTB_TAG1 1010 0000
DTB_PTE0 0010 0001
DTB_PTE1 1010 0001
DTB_ALTMODE 0010 0110
1010 0010
DTB_IA 1010 0011
DTB_IS0 0010 0100
DTB_IS1 1010 0100
DTB_ASN0 0010 0101
DTB_ASN1 1010 0101
MM_STAT 0010 0111
M_CTL 0010 1000
DC_CTL 0010 1001
DC_STAT 0010 1010
Alpha 21264/EV67 Hardware Reference Manual
MT/MF
Score- Issued
Board from Ebox
Bit Access Pipe
5 RO 0L
4 RW 0L
4 RW 0L
4 RW 0L
4 RW 0L
— RO —
4 WO 0L
— RO 0L
4 RW 0L
4 RW 0L
4 RW 0L
4 W 0L
4 WO 0L
4, 5, 6, 7 WO 0L
4, 5, 6, 7 WO 0L
1
4 W 0L
4 R 0L
4 RW 0L
2, 6 WO 0L
1, 5 WO 1L
0, 4 WO 0L
3, 7 WO 0L
6 WO 1L
7 WO 1L
7 WO 1L
6 WO 0L
7 WO 1L
4 WO 0L
7 WO 1L
— RO 0L
6 WO 0L
6 WO 0L
6 RW 0L
Latency
for
MFPR
(Cycles)
3
3
3
3
3
—
—
3
3
3
3
—
—
—
—
3
3
3
—
—
—
—
—
—
—
—
—
—
—
3
—
—
3