Operation; Cmov Decomposed - Compaq 21264 Hardware Reference Manual

The CMOV instruction is decomposed into two valid fetched instructions that, in the
absence of stalls, are fetched in consecutive cycles. See Table 6–12 for more informa-
tion.
Table 6–12 CMOV Decomposed
Instruction
CMOV Ra, Rb--> Rc

6.10.3.2 Operation

1. Setup
The following IPRs need to be set up by using PALcode instructions.
IPR Name Relevant Fields
IER_CM PCEN[1:0]
PCTX PPCE
PCTR_CTL SL0
SL1
PCTR0[19:0]
PCTR1[19:0]
I_CTL SPCE
PCT0_EN
PCT1_EN
2. Open window
PCTR0 accumulates up to 4 valid fetched instructions per cycle when enabled via
I_CTL[PCT0_EN] and either I_CTL[SPCE] or PCTX[PPCE].
The valid fetched instruction that causes PCTR0 to overflow opens the window and
becomes the
instruction was in flight. The first cycle of the window is the 5th cycle after the
instruction was fetched. A residual count of up to 7 valid fetched instructions is
accumulated in PCTR0 in the two cycles between overflow and the start of the Pro-
fileMe window. This residual count is returned in I_STAT[overcount(2,0)].
3. Count
If PCTR0 and PCTR1 are enabled, they increment according to modes selected by
SL0 & SL1.
4. End window
The last cycle of the window depends on whether the instruction traps, retires,
aborts, and/or is squashed by the fetcher.
Alpha 21264/EV67 Hardware Reference Manual
New Instructions
CMOV1 Ra, oldRc
CMOV2 newRc1, Rb
Meaning
Enable Interrupts.
Enable Process Performance Counting or use I_CTL[SPCE].
Selects Aggregate or ProfileMe mode; set to 1 for ProfileMe mode.
Selects PCTR0 and PCTR1 counting modes. See Table 6–14 for more infor-
mation.
Set counter 0 value (2**20-N). This selects approximately the Nth valid
fetched instruction as the profiled instruction. Because writes to PCTR0 are
incremented by 0..4, the profiled instruction is one of the (N-4)th to Nth valid
fetched instructions. See Section 6.10.1 for more setup precautions.
Set counter 1 value = 0. See Section 6.10.1 for more setup precautions.
Enable System Performance Counting or use PCTX[PPCE].
Enable performance counter 0.
Enable performance counter 1.
rofiled instruction and covers a period of time near to when the
p
Performance Counter Support
newRc1
newRc2
Privileged Architecture Library Code
6–21