Compaq 21264 Hardware Reference Manual page 182

Cbox CSRs and IPRs
; SET_DIRTY_ENABLE = 6
; BC_BANK_ENABLE = 1
; BC_WRT_STS = 0
;
; The value for the write_many chain is based on Table 5–25.
;
; The value is sampled from MSB, 6 bits at a time, as it is written
; to EV6__DATA. Therefore, before the value can be shifted in, it must be
; inverted on a by 6 basis. The code then writes out 6 bits at a time,
; shifting right by 6 after each write.
;
; So the following transformation is done on the write_many value:
;
; [35:30]|[29:24]|[23:18]|[17:12]|[11:06]|[05:00] =>
; [05:00]|[11:06]|[17:12]|[23:18]|[29:24]|[35:30]
;
; WRITE_MANY chain = 0x07FBFFFFD
; value to be shifted in
;
; Before the chain can be written, I_CTL[SBE] must be disabled,
; and the code must be forced into the Icache.
;
ALIGN_CACHE_BLOCK <^x47FF041F>; align with nops
mb
lda r0, ^x0086(r31)
hw_mtpr r0, EV6__I_CTL
br r0, .
addq r0, #17, r0
hw_mtpr r31, EV6__IC_FLUSH
bne r31, .
hw_jmp_stall (r0)
ALIGN_CACHE_BLOCK <^x47FF041F>
bc_config:
mb
lda r1, ^xFFC1(r31)
ldah r0, ^x7FFE(r31)
zap r1, #^x0c, r1
bis r1, r0, r1
addq r31, #6, r0
bc_config_shift_in:
hw_mtpr r1, EV6__DATA
subq r0, #1, r0
beq r0, bc_config_done
srl r1, #6, r1
br r31, bc_config_shift_in
bc_config_done:
hw_mtpr r31, <EV6__MM_STAT ! 64>
beq r31, bc_config_end
br r31, .-4
bis r31, r31, r31
bis r31, r31, r31
bc_config_end:
Internal Processor Registers
5–40
= 0xF7FFEFFC1
; wait for MEM-OP's to complete
; load I_CTL.....
; .....SDE=2, IC_EN=3, SBE=0
; create dest address
; finish computing dest address
; flush the Icache
; separate retires
; force flush
; align with nops
; pull this block in Icache
; data[15:00] = 0xFFC1
; data[31:16] = 0x7FFE
; clear out bits [31:16]
; or in bits [31:16]
; shift in 6 x 6 bits
; shift in 6 bits
; decrement R0
; done if R0 is zero
; align next 6 bits
; continue shifting
; wait until last shift
; predicts fall thru
; predict infinite loop
; nop
; nop
Alpha 21264/EV67 Hardware Reference Manual