Sysdatainvalid_L And Sysdataoutvalid_L; Four Timing Examples - Compaq 21264 Hardware Reference Manual

System Port
Table 4–27 lists information for the four timing examples. In Table 4–27, note the fol-
lowing:
•
SysDc write commands are not affected by the SYSDC_DELAY parameter.
•
The SYS_RCV_MUX_PRESET adds delay at the rate of one INT_FWD_CLK at a
time. For example, adding the delay of one bit time to system 1 adds 1.5 GCLK
cycles to the delay and drives the SysDc write command-to-data relationship from
one to two SYSCLKs.
•
For write transfers, the 21264/EV67 drivers are enabled on the preceding GCLK
BPHASE, before the start of a write transfer, and disabled on the succeeding GCLK
BPHASE at the end of the write transfer. The write data is enveloped by the 21264/
EV67 drivers to guarantee that every data transfer has the same data valid window.
Table 4–27 Four Timing Examples
System
System 1
System 2
System 3
System 4
1
The system framing clock ratio is the number of INT_FWD_CLK cycles per
SYSCLK cycles.
The four examples described here assume no skew for the 2.0X and 4.0X cases and one
bit time of skew for the 1.5X and 2.5X cases.
For system 1, the distance between SysDc and the first SYSCLK is nine GCLK cycles
but the additional delay of one bit time (1.5 GCLKs) puts the actual delay after perceiv-
ing the SysDc command to 7.5 GCLKS, which misses the 8.5 cycle constraint. There-
fore, the 21264/EV67 drives data two SYSCLKs after receiving the SysDc write
command.
For system 2, the distance between SysDc and the second SYSCLK is eight GCLK
cycles, which also misses the 8.5 cycle constraint, so the 21264/EV67 drives data three
SYSCLK cycles after receiving the SysDc write command (12 cycles).
The other two cases are derived in a similar manner.

4.7.8.4 SysDataInValid_L and SysDataOutValid_L

The SysDataValid signals (SysDataInValid_L and SysDataOutValid_L
the system and control the rate of data delivery to and from the 21264/EV67.
SysDataInValid
SysDataInValid_L signal controls the flow of data into the 21264/EV67, and may
The
be used to introduce an arbitrary number of cycles between octaword transfers into the
21264/EV67. The rules for using SysDataInValid_L follow:
Cache and External Interfaces
4–34
Bit Rate System Framing Clock Ratio
1.5X 4:1
2.0X 2:1
2.5X 2:1
4X 2:1
_
L
Alpha 21264/EV67 Hardware Reference Manual
1
Write Data
2 SYSCLKs
3 SYSCLKs
2 SYSCLKs
2 SYSCLKs
are driven by
)