E.1 Forwarding Clock Pin Groupings - Compaq 21264 Hardware Reference Manual

21264/EV67-to-Bcache Pin Interconnections
This appendix provides the pin interface between the 21264/EV67 and Bcache
SSRAMs.

E.1 Forwarding Clock Pin Groupings

Table E–1 lists the correspondance between the clock signals for the 21264/EV67 and
Bcache (late-write non-bursting and dual-data rate) SSRAMs.
Table E–1
Pad and Pin
BcData_H[71:64,7:0]
BcCheck_H[8,0]
BcData_H[79:72,15:8]
BcCheck_H[9,1]
BcData_H[87:80,23:16]
BcCheck_H[10,2]
BcData_H[95:88,31:24]
BcCheck_H[11,3]
BcData_H[103:96,39:32]
BcCheck_H[12,4]
BcData_H[111:104,47:40]
BcCheck_H[13,5]
BcData_H[119:112,55:48]
BcCheck_H[14.6]
BcData_H[127:120,63:56]
BcCheck_H[15,7]
BcTag_H[42:20]
BcTagParity_H
Alpha 21264/EV67 Hardware Reference Manual 21264/EV67-to-Bcache Pin Interconnections
Bcache Forwarding Clock Pin Groupings
Input Clock
BcDataInClk_H[0]
BcDataInClk_H[0]
BcDataInClk_H[1]
BcDataInClk_H[1]
BcDataInClk_H[2]
BcDataInClk_H[2]
BcDataInClk_H[3]
BcDataInClk_H[3]
BcDataInClk_H[4]
BcDataInClk_H[4]
BcDataInClk_H[5]
BcDataInClk_H[5]
BcDataInClk_H[6]
BcDataInClk_H[6]
BcDataInClk_H[7]
BcDataInClk_H[7]
BcTagInClk_H
BcTagInClk_H
Output Clocks
BcDataOutClk_x[0]
BcDataOutClk_x[0]
BcDataOutClk_x[0]
BcDataOutClk_x[0]
BcDataOutClk_x[1]
BcDataOutClk_x[1]
BcDataOutClk_x[1]
BcDataOutClk_x[1]
BcDataOutClk_x[2]
BcDataOutClk_x[2]
BcDataOutClk_x[2]
BcDataOutClk_x[2]
BcDataOutClk_x[3]
BcDataOutClk_x[3]
BcDataOutClk_x[3]
BcDataOutClk_x[3]
BcTagOutClk_x
BcTagOutClk_x
E
E–1