Table A–11 Exceptional Input and Output Conditions (Continued)
Alpha Instructions
SNaN operand
CVTfi OUTPUT
Inexact result
Integer overflow
CVTif OUTPUT
Inexact result
CVTff INPUT
Inf operand
QNaN operand
SNaN operand
CVTff OUTPUT (same as ADDx)
FBEQ FBNE FBLT FBLE FBGT FBGE
LDS LDT
STS STT
CPYS CPYSN
FCMOVx
See Section 2.14 for information about the floating-point control register (FPCR).
Alpha 21264/EV67 Hardware Reference Manual
IEEE Floating-Point Conformance
21264/EV67 Hardware
Supplied Result
0
Result
Truncated result
Result
±Inf
QNaN
QNaN
Alpha Instruction Set
Exception
Invalid Op
Inexact
Invalid Op
Inexact
(none)
(none)
Invalid Op
A–17