Example For Initializing Bcache - Compaq 21264 Hardware Reference Manual

Table 7–9 WRITE_MANY Chain CSR Values for Bcache Initialization
WRITE_MANY Chain CSRs
EVICT_ENABLE
BC_WRT_STS[3:0]
BC_BANK_ENABLE
Except for INIT_MODE, all the CSR registers have been described in earlier sections.
When asserted, INIT_MODE has the following behavior:
•
Cache block updates to the Dcache set the block to the Clean state.
•
Updates to the Bcache use the BC_WRT_STS[3:0] bits.
•
WrVictimBlk command generation to the system interface are squashed.
Using the INVAL_TO_DIRTY_ENABLE and INIT_MODE registers, initialization
code loaded from the SROM can generate and delete blocks inside the 21264/EV67
without system interaction. This behavior is very useful for initialization and startup
processing, when the system interfaces are not fully functional. Figure 7–4 shows a
code example for initializing Bcache.
Figure 7–4 Example for Initializing Bcache
Reset chip and load Icache with this code
set init_mode
for 2 X bc_size
{ WH64 address }
turn_off_bcache:
Alpha 21264/EV67 Hardware Reference Manual
Initialization Mode Processing
Required Value at Initialization Mode
0
0
0
;now all WrVictims are ignored
;bc_enable_a
;zeroblk_enable_a
;set_dirty_enable_a
;init_mode_a
;enable_evict_a
;bc_wrt_sts_a
;bc_bank_enable_a
;bc_size_a
;now all writes to Bcache actually invalidate
;the Bcache. (if space was needed for scratch
;pad, the status bits could just as
;well be Valid)
;This loop generates legal ECC data, and
;invalidate tags which are written to the
;Bcache for all but the final 64KB of address.
;bc_enable_a
;init_mode_a
;bc_size_a
;zeroblk_enable_a
;enable_evict_a
;set_dirty_enable_a
;bc_bank_enable_a
;bc_wrt_sts_a
Initialization and Configuration
1
1
0
1
0
0
0
15
0
0
0
1
0
0
0
0
7–13