Load Instructions To R31 And F31; Normal Prefetch: Ldbu, Ldf, Ldg, Ldl, Ldt, Ldwu, Hw_Ldl Instructions; Prefetch With Modify Intent: Lds Instruction; Instructions Retired Without Execution - Compaq 21264 Hardware Reference Manual

Table 2–6 Instructions Retired Without Execution
Instruction Type
INTA, INTL, INTM, INTS
FLTI, FLTL, FLTV
LDQ_U
MISC
FLTS

2.6 Load Instructions to R31 and F31

This section describes how the 21264/EV67 processes software-directed prefetch trans-
actions and load instructions with a destination of R31 and F31.
Prefetches allocate a MAF entry. How the MAF entry is allocated is what distinguishes
the type of prefetch. A normal prefetch is equivalent to a normal load MAF (that is, a
MAF entry that puts the block into the Dcache in a readable state). A prefetch with
modify intent is equivalent to a normal store MAF (that is, a MAF entry that puts the
block into the Dcache in a writeable state). A prefetch, evict next, is equivalent to a nor-
mal load MAF, with the additional behavior described in Section 2.6.3, below.
A prefetch is not performed if the prefetch hits in the Dcache (as if it were a normal
load).
Load operations to R31 and F31 may generate exceptions. These exceptions must be
dismissed by PALcode.
The following sections describe the operational prefetch behavior of these instructions.

2.6.1 Normal Prefetch: LDBU, LDF, LDG, LDL, LDT, LDWU, HW_LDL Instructions

The 21264/EV67 processes these instructions as normal cache line prefetches. If the
load instruction hits the Dcache, the instruction is dismissed, otherwise the addressed
cache block is allocated into the Dcache.
The HW_LDL instruction construct equates to the HW_LD instruction with the LEN
field clear. See Table 6–3.

2.6.2 Prefetch with Modify Intent: LDS Instruction

The 21264/EV67 processes an LDS instruction, with F31 as the destination, as a
prefetch with modify intent transaction (ReadBlkMod command). If the transaction hits
a dirty Dcache block, the instruction is dismissed. Otherwise, the addressed cache block
is allocated into the Dcache for write access, with its dirty and modified bits set.
Alpha 21264/EV67 Hardware Reference Manual
Load Instructions to R31 and F31
Notes
All with R31 as destination.
All with F31 as destination. MT_FPCR is not included
because it has no destination—it is never removed from the
pipeline.
All with R31 as destination.
TRAPB and EXCB are always removed. Others are never
removed.
All (SQRT, ITOF) with F31 as destination.
Internal Architecture
2–23