Exception Summary Register; Exception Summary Register Fields Description - Compaq 21264 Hardware Reference Manual

Ibox IPRs
Figure 5–20 Exception Summary Register
63
SEXT(SET_IOV)
SET_IOV
SET_INE
SET_UNF
SET_OVF
SET_DZE
SET_INV
PC_OVFL
BAD_IVA
REG[4:0]
INT
IOV
INE
UNF
FOV
DZE
INV
SWC
Table 5–9 describes the exception summary register fields.
Table 5–9 Exception Summary Register Fields Description
Name
SEXT(SET_IOV)
SET_IOV
SET_INE
SET_UNF
SET_OVF
SET_DZE
SET_INV
PC_OVFL
Reserved
BAD_IVA
Internal Processor Registers
5–14
48 47 46 45 44 43 42 41 40
Extent Type Description
[63:48] RO, 0 Sign-extended value of bit 47, SET_IOV.
[47] RO PALcode should set FPCR[IOV].
[46] RO PALcode should set FPCR[INE].
[45] RO PALcode should set FPCR[UNF].
[44] RO PALcode should set FPCR[OVF].
[43] RO PALcode should set FPCR[DZE].
[42] RO PALcode should set FPCR[INV].
[41] RO Indicates that EXC_ADDR was improperly sign extended for 48-
bit mode over/underflow IACV.
[40:14] RO, 0 Reserved for Compaq.
[13] RO Bad Istream VA.
This bit should be used by the IACV PALcode routine to deter-
mine whether the offending I-stream virtual address is latched in
the EXC_ADDR register or the VA register. If BAD_IVA is clear,
EXC_ADDR contains the address; if BAD_IVA is set, VA con-
tains the address.
Alpha 21264/EV67 Hardware Reference Manual
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