Bcache Clocking - Compaq 21264 Hardware Reference Manual

Bcache Port
Table 4–36 Bcache Port Pins (Continued)
Pin Name
BcDataWr_L
BcLoad_L
BcTag_H[42:20]
BcTagDirty_H
BcTagInClk_H
BcTagOE_L
BcTagOutClk_H
BcTagOutClk_L
BcTagParity_H
BcTagShared_H
BcTagValid_H
BcVref
BcTagWr_L

4.8.2 Bcache Clocking

For clocking, the Bcache port pins can be divided into three groups.
1. The Bcache index pins (address and control) are referenced to Int_Add_BcClk, an
internal version of the Bcache forwarded clock. The index pins are valid for the
whole period of the Int_Add_BcClk. The index pins are:
BcAdd_H[23:4]
BcDataOE_L
BcDataWr_L
BcLoad_L
BcTagOE_L
BcTagWr_L
2. The data pins, when driven as outputs, are referenced to Int_Data_BcClk, another
internal version of the Bcache forwarded clock. The data pins, when used as inputs,
can be referenced to the incoming Bcache clocks, BcDataInClk_H[7:0] and
BcTagInClk_H. Int_Data_BcClk can be delayed relative to Int_Add_BcClk from
0 to 3 GCLK cycles by using Cbox CSR BC_CPU_CLK_DELAY[1:0]. The data
pins are:
BcCheck_H[15:0]
BcData_H[127:0]
BcTag_H[42:20]
BcTagDirty_H
BcTagParity_H
Cache and External Interfaces
4–44
Type Count Reference Clock
O_PP 1 Int_Index_BcClk
O_PP 1 Int_Index_BcClk
B_DA_PP 23 Int_Data_BcClk
BcTagInClk_H
B_DA_PP 1 Int_Data_BcClk
BcTagInClk_H
I_DA 1 NA
O_PP 1 Int_Index_BcClk
O_PP 2 NA
B_DA_PP 1 Int_Data_BcClk
BcTagInClk_H
B_DA_PP 1 Int_Data_BcClk
BcTagInClk_H
B_DA_PP 1 Int_Data_BcClk
BcTagInClk_H
I_DC_REF 1 NA
O_PP 1 Int_Index_BcClk
Description
Bcache data write enable
Bcache burst enable
output Bcache tag data
input
output Bcache tag dirty bit
input
Tag input data reference clock
Bcache tag output enable/chip
select
Bcache tag clock— high and low
versions
output Bcache tag parity bit
input
output Bcache tag shared bit
input
output Bcache tag valid bit
input
Input reference voltage for tag data
Bcache data write enable
Alpha 21264/EV67 Hardware Reference Manual