Compaq 21264 Hardware Reference Manual page 100

Cache Coherency
Table 4–5 System Responses to 21264/EV67 Commands and 21264/EV67 Reactions (Continued)
21264/EV67
CMD SysDc
RdBlkModx ReadData
ReadDataShared
ReadDataShared/Dirty
RdBlkModx ReadDataDirty
RdBlkModx ChangeToDirtySuccess
ChangeToDirtyFail
RdBlkModx ReadDataError
ChxToDirty ReadData
ReadDataShared
ReadDataShared/Dirty
ChxToDirty ReadDataDirty
ChxToDirty ReadDataError
ChToDirty ChangeToDirtySuccess Normal response. ChangeToDirtySuccess makes the block writable.
ChxToDirty ChangeToDirtyFail
InvalToDirty ReadData
ReadDataShared
ReadDataShared/Dirty
InvalToDirty ReadDataError
InvalToDirty ReadDataDirty
ChangeToDirtySuccess
Cache and External Interfaces
4–12
21264/EV67 Action
The cache block is filled and marked with a nonwritable status. If the
store instruction that generated the RdBlkModx command is still
active (not killed), the 21264/EV67 will retry the instruction, generat-
ing the appropriate ChangeToDirty command. Succeeding store com-
mands cannot update the block without external reference.
The 21264/EV67 performs a normal fill response, and the cache block
becomes writable.
Both SysDc responses are illegal for read/modify commands.
The cache block command was to NXM address space. The 21264/
EV67 delivers an all-ones pattern to any dependent load command,
forces a fail action on any pending store commands to this block, and
any store to this block is not retried. The Cbox evicts the cache block
from the cache system (with associated victim processing). The cache
block is marked invalid.
The original data in the Dcache is replaced with the filled data. The
block is not writable, so the 21264/EV67 will retry the store instruc-
tion and generate another ChxToDirty class command. To avoid a
potential livelock situation, the STC_ENABLE CSR bit must be set.
Any STx_C instruction to this block is forced to fail. In addition, a
Shared/Dirty response causes the 21264/EV67 to generate a victim
for this block upon eviction.
The data in the Dcache is replaced with the filled data. The block is
writable, so the store instruction that generated the original command
can update this block. Any STx_C instruction to this block is forced
to fail. In addition, the 21264/EV67 generates a victim for this block
upon eviction.
Impossible situation. The block must be cached to generate a ChxTo-
Dirty command. Caching the block is not possible because all NXM
fills are filled noncached.
The 21264/EV67 retries the store instruction and updates the Dcache.
Any STx_C instruction associated with this block is allowed to suc-
ceed.
The MAF entry is retired. Any STx_C instruction associated with the
block is forced to fail. If a STx instruction generated this block, the
21264/EV67 retries and generates either a RdBlkModx (because the
reference that failed the ChangeToDirty also invalidated the cache by
way of an invalidating probe) or another ChxToDirty command.
The block is not writable, so the 21264/EV67 will retry the WH64
instruction and generate a ChxToDirty command.
The 21264/EV67 doesn't send InvalToDirty commands offchip spec-
ulatively. This NXM condition is a hard error. Systems should per-
form a machine check.
The block is writable. Done.
Alpha 21264/EV67 Hardware Reference Manual