Ac Specifications - Compaq 21264 Hardware Reference Manual

Compaq microprocessor reference manual
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The input voltage swing is Vref ± 0.40 Volts.
All output skew data is based on simulation into a 50-ohm transmission line that is
terminated with 50 ohms to VDD/2 for Bcache timing, and with 50 ohms to VDD
for all other timing.
Timings are measured at the pins as follows:
Table 9–13 AC Specifications
Signal Name
Type
SysAddIn_L[14:0
I_DA
SysFillValid_L
I_DA
SysDataInValid_L
I_DA
SysDataOutValid_L
I_DA
SysAddInClk_L
I_DA
SysAddOut_L[14:0]
O_OD
SysAddOutClk_L
O_OD
SysData_L[63:0]
B_DA_OD
SysCheck_L[7:0]
B_DA_OD
SysDataInClk_H[7:0]
I_DA
SysDataOutClk_L[7:0]
O_OD
BcAdd_H[23:4]
O_PP
BcDataOE_L
O_PP
BcLoad_L
O_PP
BcDataWr_L
O_PP
BcData_H[127:0]
B_DA_PP
BcDataInClk_H[7:0]
I_DA
BcDataOutClk_H[3:0]
O_PP
BcDataOutClk_L[3:0]
O_PP
BcTag_H[42:20]
B_DA_PP
BcTagDirty_H
B_DA_PP
BcTagParity_H
B_DA_PP
Alpha 21264/EV67 Hardware Reference Manual
For open-drain outputs, timing is measured to (V
the offchip termination voltage for system signals.
For non-open-drain outputs, timing is measured to (V
For all inputs other than type I_DA_CLK, timing is measured to the point
where the input signal crosses VREF.
For type I_DA_CLK inputs, timing is measured when the voltage on the com-
plementary inputs is equal.
Reference Signal
SysAddInClk_L
SysAddInClk_L
SysAddInClk_L
SysAddInClk_L
NA
SysAddOutClk_L
EV6Clk_x
SysDataInClk_H[7:0]
SysDataOutClk_L[7:0]
SysDataInClk_H[7:0]
SysDataOutClk_L[7:0]
NA
EV6Clk_x
BcTagOutClk_x
BcDataOutClk_x[3:0]
BcDataOutClk_x[3:0]
BcDataInClk_H[7:0]
NA
EV6Clk_x
EV6Clk_x
BcTagInClk_H
BcTagInClk_H
BcTagInClk_H
+ V
ol
1
2
TSU
TDH
TSkew
400 ps
400 ps
NA
400 ps
400 ps
NA
400 ps
400 ps
NA
400 ps
400 ps
NA
NA
NA
NA
NA
NA
± 300 ps
NA
NA
± 400 ps
400 ps
400 ps
NA
4
NA
NA
± 300 ps
400 ps
400 ps
NA
4
NA
NA
± 300 ps
NA
NA
NA
NA
NA
± 400 ps
NA
NA
± 300 ps
7
10
NA
NA
± 300 ps
400 ps
400 ps
NA
NA
NA
NA
NA
NA
± 400 ps
NA
NA
± 400 ps
400 ps
400 ps
NA
400 ps
400 ps
NA
400 ps
400 ps
NA
AC Characteristics
)/2. Where V
is
term
term
+ V
)/2.
ol
oh
Duty Cycle
TSlew
NA
1.0 V/ns
NA
1.0 V/ns
NA
1.0 V/ns
NA
1.0 V/ns
45–55%
1.0 V/ns
3
NA
NA
45-55%
NA
NA
1.0 V/ns
3
NA
NA
NA
1.0 V/ns
3
NA
NA
45-55%
1.0 V/ns
45-55%
NA
5,6
NA
45-55%
8
38-63%
9
40-60%
6
45-55%
1.0 V/ns
8
38-63%
NA
9
40-60%
NA
NA
NA
45-55%
NA
1.0 V/ns
NA
1.0 V/ns
NA
1.0 V/ns
Electrical Data
9–7

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