Double-Bit Fill Errors; Error Case Summary - Compaq 21264 Hardware Reference Manual

8.11 Double-Bit Fill Errors

Double-bit errors for fills are detected, but not corrected, in the 21264/EV67. The fol-
lowing events may cause a double-bit fill error:
•
Icache fill from Bcache
•
Dcache fill from Bcache
•
Icache fill from memory
•
Dcache fill from memory
If an error is detected, the following actions are taken:
•
C_STAT is set to one of the following:
ISTREAM_BC_DBL (Icache fill from Bcache)
DSTEAM_BC_DBL (Dcache fill from Bcache)
ISTREAM_MEM_DBL (Icache fill from memory)
DSTREAM_MEM_DBL (Dcache fill from memory)
•
C_ADDR contains bits [42:6] of the system memory fill address of the block that
contains the error.
•
When enabled, a machine check (MCHK) is posted. The MCHK is taken when not
in PALmode.
•
A double-bit fill error from memory, marked by the data's corresponding ECC,
when written to cache, also writes the corresponding ECC to cache. Any consumer
of that error (such as another CPU) also consumes the corresponding ECC value.
Note:

8.12 Error Case Summary

Table 8–3 summarizes the various error cases and their ramifications.
Table 8–3 Error Case Summary
Error Exception Status
Icache data or tag CRD
parity error
Dcache tag parity DFAULT
error (on issue)
Dcache tag parity MCHK
error (on retry)
Dcache single-bit CRD
ECC error on load
Alpha 21264/EV67 Hardware Reference Manual
C_ADDR may be inaccurate in heavy traffic conditions. C_STAT is accu-
rate.
ISTAT[PAR]
MM_STAT[DC_TAG_PERR]
VA[address]
1
DC_STAT[TPERR_P0] or
DC_STAT[TPERR_P1]
DC_STAT[ECC_ERR_LD]
C_STAT[DSTREAM_DC_ERR]
C_ADDR[bits [19:6] of the error
address. [42:20] not updated.]
Double-Bit Fill Errors
Hardware
Action PALcode Action
Icache flushed Log as CRD
— Evict with two
HW_LDs and log as
CRD
— Log as MCHK
Corrected and Log as CRD
scrubbed
Error Detection and Error Handling
8–9