Floating-Point Divide/Square Root Early Retire; Retire Of Operate Instructions Into R31/F31 - Compaq 21264 Hardware Reference Manual

Retire of Operate Instructions into R31/F31

Table 2–5 Minimum Retire Latencies for Instruction Classes (Continued)
Instruction Class
Floating-point DIV/SQRT
Floating-point conditional
branch
BSR/JSR

2.4.1 Floating-Point Divide/Square Root Early Retire

The floating-point divider and square root unit can detect that, for many combinations
of source operand values, no exception can be generated. Instructions with these oper-
ands can be retired before the result is generated. When detected, they are retired with
the same latency as the FP add class. Early retirement is not possible for the following
instruction/operand/architecture state conditions:
•
Instruction is not a DIV or SQRT.
•
SQRT source operand is negative.
•
Divide operand exponent_a is 0.
•
Either operand is NaN or INF.
•
Divide operand exponent_b is 0.
•
Trapping mode is /I (inexact).
•
INE status bit is 0.
Early retirement is also not possible for divide instructions if the resulting exponent has
any of the following characteristics (EXP is the result exponent):
•
DIVT, DIVG: (EXP >= 3FF
•
DIVS, DIVF: (EXP >= 7F
2.5 Retire of Operate Instructions into R31/F31
Many instructions that have R31 or F31 as their destination are retired immediately
upon decode (stage 3). These instructions do not produce a result and are removed from
the pipeline as well. They do not occupy a slot in the issue queues and do not occupy a
functional unit. Table 2–6 lists these instructions and some of their characteristics. The
instruction type in Table 2–6 is from Table C-6 in Appendix C of the Alpha Architecture
Handbook, Version 4.
Internal Architecture
2–22
Retire Stage Comments
11 + latency Add latency of unit reuse for the instruction indicated in Table
2–4. For example, latency for a single-precision fdiv would be
11 plus 9 from Table 2–4. Latency is 11 if hardware detects that
no exception is possible (see Section 2.4.1).
11 Branch instruction mispredict is reported in stage 7.
10 JSR instruction mispredict is reported in stage 8.
) OR (EXP <= 2
16
) OR (EXP <= 382
16
)
16
)
16
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