Compaq 21264 Hardware Reference Manual page 304

Restriction 1 : Reset Sequence Required by Retire Logic and Mapper
br r31,bccshf
bccend:mtpr
addq r31,r31,r0
addq r31,r31,r1
mtpr r31,EV6__EXC_ADDR + 16
beq r31, bccnxt
br r31, .-4
addq r31,r31,r1
bccnxt:addq r31,4,r0
mtpr r0,EV6__PROCESS_CONTEXT
lda r0,DC_CTL_INIT_K(r31)
mtpr r0,EV6__DC_CTL
addq r31,r31,r0
addq r31,r31,r1
lda r0,0xff61(r31)
zap r0,0xfc,r0
mtpr r31,EV6__DTB_TAG0 /* write DTB_TAG0 (SCRBRD=2,6)*/
mtpr r31,EV6__DTB_TAG1 /* write DTB_TAG1 (SCRBRD=1,5)*/
mtpr r0,EV6__DTB_PTE0
mtpr r0,EV6__DTB_PTE1
mtpr r31,EV6__SIRR
lda r0,0x08FF(r31)
sll r0,52,r0
itoft r0, f0
mt_fpcr f0
lda r0,0x2086(r31)
ldah r0,0x0050(r0)
mtpr r0,EV6__I_CTL
mtpr r31,EV6__CC
lda r0,0x001F(r31)
sll r0,28,r0
mtpr r0,EV6__HW_INT_CLR/* clear bits in HW_INT_CLR (SCRBRD=4)*/
mtpr r0,EV6__I_STAT
lda r0,0x001F(r31)
mtpr r0,EV6__DC_STAT
addq r31,r31,r0
mtpr r31,EV6__PCTR_CTL /* 1st buffer fetch block for above map-stall
bis r31,1,r0
bis r31,1,r0
mulq/v r31,r31,r0
PALcode Restrictions and Guidelines
D–6
r31,EV6__EXC_ADDR + 16/* dummy IPR write - sets SCBD bit 4 */
/* predicts fall through in PALmode*/
/* fools ibox predictor into infinite loop*/
/* nop*/
/* load PCTX.....*/
/* .....ECC_EN=0, FHIT=0, SET_EN=3
/* (SCRBRD=6)*/
/* nop*/
/* nop*/
/* R0 = ^xff61 (superpage) */
/* PTE protection for DTB write in next
block*/
/* write DTB_PTE0 (SCRBRD=0,4)*/
/* write DTB_PTE1 (SCRBRD=3,7)*/
/* clear SIRR (SCRBRD=4)*/
/* load FPCR.....*/
/* .....initial FPCR value*/
/* nop
/* nop
/* load I_CTL.....*/
/* .....TB_MB_EN=1, CALL_PAL_R23=1, SL_XMIT=1,
/* SBE=0, SDE=2, IC_EN=3*/
/* value = 0x0000000000502086 (SCRBRD=4)*/
/* clear CC (SCRBRD=5)*/
/* write-one-to-clear bits in HW_INT_CLR,
/* I_STAT and DC_STAT*/
/* value = 0x00000001F0000000*/
/* clear bits in I_STAT
/*(SCRBRD=4) creates a map-stall
/* under the above mtpr to SCRBRD=4*/
/* value = 0x000000000000001F*/
/* clear bits in DC_STAT (SCRBRD=6)*/
/* nop*/
/* and 1st clear PCTR_CTL (SCRBRD=4)*/
/* set up value for demon write*/
/* set up value for demon write*/
/* nop*/
/* continue shifting*/
/* nop*/
/* nop*/
/* also a dummy IPR write -
/* stalls until above write
/* retires*/
/* ..... FPE=1 (SCRBRD=4)*/
/* load DC_CTL.....*/
itoftr0,f0 ; value = 0x8FF0000000000000*/
mt_fpcrf0,f0,f0 ; do the load*/
Alpha 21264/EV67 Hardware Reference Manual