3.2 21264/EV67 Signal Names and Functions
Table 3–1 defines the 21264/EV67 signal types referred to in this section.
Table 3–1 Signal Pin Types Definitions
Signal Type
Inputs
I_DC_REF
I_DA
I_DA_CLK
Outputs
O_OD
O_OD_TP
O_PP
O_PP_CLK
Bidirectional
B_DA_OD
B_DA_PP
Other
Spare
NoConnect
1
All Spare connections are Reserved to Compaq to maintain compatibility between
passes of the chip. Designers should not use these pins.
Table 3–2 lists all signal pins in alphabetic order and provides a full functional descrip-
tion of the pins. Table 3–4 lists the signal pins and their corresponding pin grid array
(PGA) locations in alphabetic order for the signal type. Table 3–5 lists the pin grid array
locations in alphabetical order.
Table 3–2 21264/EV67 Signal Descriptions
Signal
BcAdd_H[23:4]
BcCheck_H[15:0]
BcData_H[127:0]
BcDataInClk_H[7:0]
BcDataOE_L
Alpha 21264/EV67 Hardware Reference Manual
Definition
Input DC reference pin
Input differential amplifier receiver
Input clock pin
Open drain output driver
Open drain driver for test pins
Push/pull output driver
Push/pull output clock driver
Bidirectional differential amplifier receiver with open drain output
Bidirectional differential amplifier receiver with push/pull output
Reserved to Compaq
No connection — Do not connect to these pins for any revision of the
21264/EV67. These pins must float.
Type
Count
Description
O_PP
20
These signals provide the index to the Bcache.
B_DA_PP
16
ECC check bits for BcData_H[127:0].
B_DA_PP
128
Bcache data signals.
I_DA
8
Bcache data input clocks. These clocks are used with high
speed SDRAMs, such as DDRs, that provide a clock-out with
data-output pins to optimize Bcache read bandwidths. The
21264/EV67 internally synchronizes the data to its logic with
clock forward receive circuits similar to the system interface.
O_PP
1
Bcache data output enable. The 21264/EV67 asserts this signal
during Bcache read operations.
21264/EV67 Signal Names and Functions
1
Hardware Interface
3–3
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