Compaq 21264 Hardware Reference Manual page 73

Table 3–2 21264/EV67 Signal Descriptions (Continued)
Signal
FrameClk_H
FrameClk_L
IRQ_H[5:0]
MiscVref
PllBypass_H
PLL_VDD
Reset_L
SromClk_H
SromData_H
SromOE_L
SysAddIn_L[14:0]
SysAddInClk_L
SysAddOut_L[14:0]
SysAddOutClk_L
SysCheck_L[7:0]
SysData_L[63:0]
SysDataInClk_H[7:0]
SysDataInValid_L
SysDataOutClk_L[7:0] O_OD
SysDataOutValid_L
SysFillValid_L
Alpha 21264/EV67 Hardware Reference Manual
Type Count Description
I_DA_CLK 2 A skew-controlled differential 50% duty cycle copy of the sys-
tem clock. It is used by the 21264/EV67 as a reference, or
framing, clock.
I_DA 6 These six interrupt signal lines may be asserted by the system.
The response of the 21264/EV67 is determined by the system
software.
I_DC_REF 1 Voltage reference for the miscellaneous pins
(see Table 3–3).
I_DA 1 When asserted, this signal will cause the two input clocks
(ClkIn_x) to be applied to the 21264/EV67 internal circuits,
instead of the 21264/EV67 global clock (GCLK).
3.3 V 1 3.3-V dedicated power supply for the 21264/EV67 PLL.
I_DA 1 System reset. This signal protects the 21264/EV67 from dam-
age during initial power-up. It must be asserted until
DCOK_H is asserted. After that, it is deasserted and the
21264/EV67 begins its reset sequence.
O_OD_TP 1 Serial ROM clock. Supplies the clock that causes the SROM to
advance to the next bit. The cycle time for this clock is 256
times the cycle time of the GCLK (internal 21264/EV67
clock).
I_DA 1 Serial ROM data. Input data line from the SROM.
O_OD_TP 1 Serial ROM enable. Supplies the output enable to the SROM.
I_DA 15 Time-multiplexed command/address/ID/Ack from system to
the 21264/EV67.
I_DA 1 Single-ended forwarded clock from system for
SysAddIn_L[14:0] and SysFillValid_L.
O_OD 15 Time-multiplexed command/address/ID/mask from the 21264/
EV67 to the system bus.
O_OD 1 Single-ended forwarded clock output for
SysAddOut_L[14:0].
B_DA_OD 8 Quadword ECC check bits for SysData_L[63:0].
B_DA_OD 64 Data bus for memory and I/O data.
I_DA 8 Single-ended system-generated clocks for clock forwarded
input system data.
I_DA 1 When asserted, marks a valid data cycle for data transfers to
the 21264/EV67.
8 Single-ended 21264/EV67-generated clocks for clock for-
warded output system data.
I_DA 1 When asserted, marks a valid data cycle for data transfers from
the 21264/EV67.
I_DA 1 When asserted, this bit indicates validation for the cache fill
delivered in the previous system SysDc command.
21264/EV67 Signal Names and Functions
Hardware Interface
3–5