Bcache Transactions; Bcache Data Read And Tag Read Transactions; Data-Sample/Drive Cbox Csrs - Compaq 21264 Hardware Reference Manual

Table 4–40 Program Values to Set the Cache Clock Period (Dual-Data Rate) (Continued)
Bcache
Transfer BC_CLK_LD_VECTOR
4.0X-DD 0F0F
5.0X-DD 7C1F
6.0X-DD F03F
7.0X-DD C07F
8.0X-DD 00FF
1
These are hexadecimal values.
In addition to programming the clock CSRs, the data-sample/drive Cbox CSRs, at the
pads, must be set appropriately. Table 4–41 lists these CSRs and provides their pro-
grammed value.
Table 4–41 Data-Sample/Drive Cbox CSRs
CBOX CSR
BC_DDM_FALL_EN[0]
BC_TAG_DDM_FALL_EN[0]
BC_DDM_RISE_EN[0]
BC_TAG_DDM_RISE_EN[0]
BC_DDMF_ENABLE[0]
BC_DDMR_ENABLE[0]
BC_FRM_CLK[0]
BC_CLKFWD_ENABLE[0]

4.8.3 Bcache Transactions

The Cbox uses the programmed clock values to start data read, tag read, data write, and
tag write transactions on the rising edge of a Bcache clock. The Cbox can also be con-
figured to introduce a programmable number of bubbles when changing between write
and read commands. The following three sections describe these Bcache transactions.

4.8.3.1 Bcache Data Read and Tag Read Transactions

The 21264/EV67 always reads four pieces of data (64 bytes) from the Bcache during a
data read transaction, and always interrogates the tag array on the first cycle. Once
started, data read transactions are never cancelled. Assuming that the appropriate values
Alpha 21264/EV67 Hardware Reference Manual
1
BC_BPHASE_LD_VECTOR
0
0
0
0
0
Description
Enables the update of the 21264/EV67's Bcache outputs referenced to the
falling edge of the Bcache forwarded clock. Dual-data RAMs assert this
CSR.
Enables the update of the 21264/EV67's Bcache tag outputs referenced to the
falling edge of the Bcache forwarded clock. Alway deasserted.
Enables the update of the 21264/EV67's Bcache outputs referenced to the ris-
ing edge of the Bcache forwarded clock. Always asserted.
Enables the update of the 21264/EV67's Bcache tag outputs referenced to the
rising edge of the Bcache forwarded clock. Always asserted.
Enables the rising edge of the Bcache forwarded clock. Always asserted.
Enables the falling edge of the Bcache forwarded clock. Always asserted.
Forces the 21264/EV67 to only start Bcache transactions on the rising edge
of Bcache clocks that also coincide with the rising edge of GCLK. Must be
asserted for all dual-data parts and single-data parts at 2.5X and 3.5X.
Enables clock forward enable. Always asserted.
Bcache Port
1 1
BC_FDBK_EN
01
40
10
04
01
Cache and External Interfaces
4–47