Compaq 21264 Hardware Reference Manual page 28

21264/EV67 Microprocessor Features
•
An onchip, duplicate tag array used to maintain level 2 cache coherency.
•
A 64-bit data bus with onchip parity and error correction code (ECC) support.
•
Support for an external second-level (Bcache) cache. The size and some timing
parameters of the Bcache are programmable.
•
An internal clock generator providing a high-speed clock used by the 21264/EV67,
and two clocks for use by the CPU module.
•
Onchip performance counters to measure and analyze CPU and system perfor-
mance.
•
Chip and module level test support, including an instruction cache test interface to
support chip and module level testing.
•
A 2.0-V external interface.
Refer to Chapter 9 for 21264/EV67 dc and ac electrical characteristics. Refer to the
Alpha Architecture Handbook, Version 4
implementation-dependent information.
Introduction
1–4
Appendix E, for waivers and any other
,
Alpha 21264/EV67 Hardware Reference Manual