Compaq Alpha EV67 Manuals

Manuals and User Guides for Compaq Alpha EV67. We have 1 Compaq Alpha EV67 manual available for free PDF download: Hardware Reference Manual

Compaq Alpha EV67 Hardware Reference Manual

Compaq Alpha EV67 Hardware Reference Manual (356 pages)

Compaq Microprocessor Reference Manual

Brand: Compaq | Category: Computer Hardware | Size: 4.18 MB

Table of Contents

Reference Manual
1
Table of Contents
3
Internal Architecture
17
Terminology and Conventions
19
1 Introduction

25
- The Architecture
  25
- Addressing
  26
  - Integer Data Types
    26
  - Floating-Point Data Types
    26
- 21264/EV67 Microprocessor Features
  27
2 Internal Architecture

29
3 Hardware Interface

69
4 Cache and External Interfaces

89
- Introduction to the External Interfaces
  89
  - System Interface
    91
- EV67 System and Bcache Interfaces
  91
- Translation of Internal References to External Interface Reference
  93
  - Bcache Structure
    95
    
    Bcache Interface Signals
    95
    
    System Duplicate Tag Stores
    95
- EV67 Bcache Interface Signals
  95
  - Victim Data Buffer
    96
  - Cache Coherency
    96
  - Cache Coherency Basics
    96
    
    Cache Block States
    97
- Cache Subset Hierarchy
  97
  - EV67-Supported Cache Block States
    97
  - Cache Block State Transitions
    98
- System Responses to 21264/EV67 Commands
  98
  - Using Sysdc Commands
    99
- System Responses to 21264/EV67 Commands and 21264/EV67 Reactions
  99
  - Dcache States and Duplicate Tags
    101
  - Lock Mechanism
    102
    
    In-Order Processing of Ldx_L/Stx_C Instructions
    103
    
    Internal Eviction of Ldx_L Blocks
    103
    
    Liveness and Fairness
    103
    
    Managing Speculative Store Issues with Multiprocessor Systems
    104
  - System Port
    104
    
    System Port Pins
    105
- System Interface Signals
  105
- Programming the System Interface Clocks
  106
- Programming Values for System Interface Clocks
  106
- Program Values for Data-Sample/Drive Csrs
  106
  - 21264/EV67-To-System Commands
    107
    
    Bank Interleave on Cache Block Boundary Mode
    107
- Forwarded Clocks and Frame Clock Ratio
  107
- Bank Interleave on Cache Block Boundary Mode of Operation
  107
  - Page Hit Mode
    108
- Page Hit Mode of Operation
  108
- EV67-To-System Command Fields Definitions
  108
  - 21264/EV67-To-System Commands Descriptions
    109
- Maximum Physical Address for Short Bus Format
  109
- Programming INVAL_TO_DIRTY_ENABLE[1:0]
  111
  - Proberesponse Commands (Command[4:0] = 00001)
    112
- Programming SET_DIRTY_ENABLE[2:0]
  112
- EV67 Proberesponse Command
  112
  - Sysack and 21264/EV67-To-System Commands Flow Control
    113
- Proberesponse Fields Descriptions
  113
  - System-To-21264/EV67 Commands
    114
    
    Probe Commands (Four Cycles)
    114
- System-To-21264/EV67 Probe Commands
  114
- System-To-21264/EV67 Probe Commands Fields Descriptions
  115
- Data Movement Selection by Probe[4:3]
  115
- Next Cache Block State Selection by Probe[2:0]
  115
  - Data Transfer Commands (Two Cycles)
    116
- Data Transfer Command Format
  116
- Sysdc[4:0] Field Description
  117
  - Data Movement in and out of the 21264/EV67
    118
    
    21264/EV67 Clock Basics
    118
    
    Fast Data Mode
    119
- Fast Transfer Timing Example
  120
- SYSCLK Cycles between Sysaddout and Sysdata
  120
  - Fast Data Disable Mode
    121
- Cbox CSR SYSDC_DELAY[4:0] Examples
  121
  - Sysdatainvalid_L and Sysdataoutvalid_L
    122
- Four Timing Examples
  122
  - Sysfillvalid_L
    123
  - Data Wrapping
    124
- Sysfillvalid_L Timing
  124
- Data Wrapping Rules
  124
- System Wrap and Deliver Data
  125
- Wrap Interleave Order
  125
  - Nonexistent Memory Processing
    126
- Wrap Order for Double-Pumped Data Transfers
  126
- EV67 Commands with NXM Addresses and System Response
  127
  - Ordering of System Port Transactions
    128
    
    21264/EV67 Commands and System Probes
    128
- 21264/EV67 Response to System Probe and In-Flight Command Interaction
  129
  - System Probes and Sysdc Commands
    130
  - Bcache Port
    130
    
    Bcache Port Pins
    130
- Rules for System Control of Cache Status Update Order
  130
  - Bcache Port Pins
    131
- Range of Maximum Bcache Clock Ratios
  131
  - Bcache Clocking
    132
    
    Setting the Period of the Cache Clock
    133
- BC_CPU_CLK_DELAY[1:0] Values
  133
- BC_CLK_DELAY[1:0] Values
  133
- Program Values to Set the Cache Clock Period (Single-Data)
  134
- Program Values to Set the Cache Clock Period (Dual-Data Rate)
  134
  - Bcache Transactions
    135
    
    Bcache Data Read and Tag Read Transactions
    135
- Data-Sample/Drive Cbox Csrs
  135
  - Bcache Data Write Transactions
    136
  - Bubbles on the Bcache Data Bus
    137
  - Pin Descriptions
    139
    
    Bcadd_H[23:4]
    139
- Programming the Bcache to Support each Size of the Bcache
  139
  - Bcache Control Pins
    140
- Programming the Bcache Control Pins
  140
- Control Pin Assertion for RAM_TYPE a
  140
- Control Pin Assertion for RAM_TYPE B
  140
  - Bcdatainclk_H and Bctaginclk_H
    141
- Control Pin Assertion for RAM_TYPE C
  141
- Control Pin Assertion for RAM_TYPE D
  141
  - Bcache Banking
    142
  - Disabling the Bcache for Debugging
    142
  - Interrupts
    142
- Internal Processor Registers
  143
  - Ebox Iprs
    145
    
    Cycle Counter Control Register - CC_CTL
    145
    
    Cycle Counter Register - CC
    145
5 Internal Processor Registers

145
6 Privileged Architecture Library Code

185
- Palcode Description
  185
- Required Palcode Function Codes
  185
  - Palmode Environment
    186
  - Required Palcode Function Codes
    187
  - Opcodes Reserved for Palcode
    187
    
    HW_LD Instruction
    187
    
    HW_ST Instruction
    188
- HW_LD Instruction Format
  188
- HW_ST Instruction Format
  188
- Opcodes Reserved for Palcode
  188
- HW_LD Instruction Fields Descriptions
  188
  - HW_RET Instruction
    189
- HW_ST Instruction Fields Descriptions
  189
  - HW_MFPR and HW_MTPR Instructions
    190
- HW_RET Instruction Format
  190
- HW_MFPR and HW_MTPR Instructions Format
  190
- HW_RET Instruction Fields Descriptions
  190
  - Internal Processor Register Access Mechanisms
    191
- HW_MFPR and HW_MTPR Instructions Fields Descriptions
  191
- Paired Instruction Fetch Order
  193
  - Correct Ordering of Explicit Writers Followed by Implicit Readers
    194
  - Correct Ordering of Explicit Readers Followed by Implicit Writers
    195
  - Palshadow Registers
    195
  - Palcode Emulation of the FPCR
    195
    
    Status Flags
    196
  - Mf_Fpcr
    196
  - Mt_Fpcr
    196
  - Palcode Entry Points
    196
    
    CALL_PAL Entry Points
    196
    
    Palcode Exception Entry Points
    197
- Palcode Exception Entry Locations
  197
  - Translation Buffer (TB) Fill Flows
    198
    
    DTB Fill
    198
- Single-Miss DTB Instructions Flow Example
  198
  - ITB Fill
    200
- ITB Miss Instructions Flow Example
  200
  - Performance Counter Support
    201
  - General Precautions
    202
  - Aggregate Mode Programming Guidelines
    202
    
    Aggregate Mode Precautions
    202
- Iprs Used for Performance Counter Support
  202
  - Operation
    203
- Aggregate Mode Returned IPR Contents
  203
  - Aggregate Counting Mode Description
    204
    
    Bcache Miss or Long Latency Probes Cycles
    204
    
    Counter Modes for Aggregate Mode
    204
    
    Cycle Counting
    204
    
    Mbox Replay Traps Cycles
    204
    
    Retired Instructions Cycles
    204
  - Profileme Mode Programming Guidelines
    204
    
    Profileme Mode Precautions
    204
- Aggregate Mode Performance Counter IPR Input Select Fields
  204
  - Operation
    205
- CMOV Decomposed
  205
- Profileme Mode Returned IPR Contents
  206
  - Profileme Counting Mode Description
    207
    
    Bcache Miss or Long Latency Probes Cycles
    207
    
    Cycle Counting
    207
    
    Inum Retire Delay Cycles
    207
    
    Mbox Replay Traps Cycles
    207
    
    Retired Instructions Cycles
    207
    
    Counter Modes for Profileme Mode
    208
- Profileme Mode PCTR_CTL Input Select Fields
  208
7 Initialization and Configuration

209
8 Error Detection and Error Handling

229
- EV67 Error Detection Mechanisms
  229
  - Data Error Correction Code
    230
  - Icache Data or Tag Parity Error
    230
  - Dcache Tag Parity Error
    230
- Bit Data and Check Bit ECC Code
  230
  - Dcache Data Single-Bit Correctable ECC Error
    231
  - Store Instruction (Quadword or Smaller)
    232
    
    Dcache Victim Extracts
    232
  - Dcache Store Second Error
    232
  - Dcache Duplicate Tag Parity Error
    232
  - Bcache Tag Parity Error
    233
  - Bcache Data Single-Bit Correctable ECC Error
    233
    
    Icache Fill from Bcache
    233
    
    Bcache Victim Read
    234
    
    Bcache Victim Read During a Dcache/Bcache Miss
    234
    
    Dcache Fill from Bcache
    234
    
    Bcache Victim Read During an ECB Instruction
    235
  - Memory/System Port Single-Bit Data Correctable ECC Error
    235
    
    Dcache Fill from Memory
    235
    
    Icache Fill from Memory
    235
  - Bcache Data Single-Bit Correctable ECC Error on a Probe
    236
  - Double-Bit Fill Errors
    237
  - Error Case Summary
    237
- Error Case Summary
  238
9 Electrical Data

241
10 Thermal Management

251
- Operating Temperature
  251
- Heat Sink Specifications
  251
- Operating Temperature at Heat Sink Center (Tc)
  251
- Type 1 Heat Sink
  254
- Type 2 Heat Sink
  255
- Type 3 Heat Sink
  256
  - Thermal Design Considerations
    257
11 Testability and Diagnostics

259
- Test Pins
  259
- Dedicated Test Port Pins
  259
  - Srom/Serial Diagnostic Terminal Port
    260
  - SROM Load Operation
    260
  - Serial Terminal Port
    260
  - IEEE 1149.1 Port
    261
- IEEE 1149.1 Instructions and Opcodes
  261
  - Teststat_H Pin
    262
- TAP Controller State Machine
  262
  - Power-Up Self-Test and Initialization
    263
  - Built-In Self-Test
    263
  - SROM Initialization
    263
- Teststat_H Pin Timing During Power-Up Built-In Self-Test (Bist)
  263
- Teststat_H Pin Timing During Built-In Self-Initialization (Bisi)
  263
  - Serial Instruction Cache Load Operation
    264
- SROM Content Map
  264
  - Notes on IEEE 1149.1 Operation and Compliance
    265
- Icache Bit Fields in an SROM Line
  265
Alpha Instruction Set

267
- A.1 Alpha Instruction Summary
  267
- Instruction Format and Opcode Notation
  267
  - Alpha Instruction Summary
    268
- Architecture Instructions
  268
  - A–2 Architecture Instructions
    268
  - Reserved Opcodes
    274
    
    A.2 Reserved Opcodes
    274
    
    Opcodes Reserved for Palcode
    275
  - IEEE Floating-Point Instructions
    275
- IEEE Floating-Point Instruction Function Codes
  275
  - VAX Floating-Point Instructions
    277
  - Independent Floating-Point Instructions
    277
- VAX Floating-Point Instruction Function Codes
  277
  - Opcode Summary
    278
  - A.6 Opcode Summary
    278
- Independent Floating-Point Instruction Function Codes
  278
  - A–8 Opcode Summary
    278
  - Required Palcode Function Codes
    279
- Key to Opcode Summary Used in Table
  279
  - IEEE Floating-Point Conformance
    280
- Exceptional Input and Output Conditions
  281
21264/EV67 Boundary-Scan Register

285
- B.1.1 BSDL Description of the Alpha 21264/EV67 Boundary-Scan Register
  285
- Boundary-Scan Register
  286
Serial Icache Load Predecode Values

297
Palcode Restrictions and Guidelines

299

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