Compaq 21264 Hardware Reference Manual page 223

Table 7–10 Internal Processor Registers at Power-Up Reset State (Continued)
Mnemonic Register Name
ITB_IAP ITB invalidate-all (ASM=0)
ITB_IA ITB invalidate all
ITB_IS ITB invalidate single
PMPC ProfileMePC
EXC_ADDR Exception address
IVA_FORM Instruction VA format
IER_CM Interrupt enable current mode
SIRR Software interrupt request
ISUM Interrupt summary
HW_INT_CLR Hardware interrupt clear
EXC_SUM Exception summary
PAL_BASE PAL base address
I_CTL Ibox control
I_STAT Ibox status
IC_FLUSH Icache flush
CLR_MAP Clear virtual-to-physical map
SLEEP Sleep mode
PCTX Ibox process context
PCTR_CTL Performance counter control
Ebox IPRs
CC Cycle counter
CC_CTL Cycle counter control
VA Virtual address
VA_FORM Virtual address format
VA_CTL Virtual address control
Mbox IPRs
DTB_TAG0 DTB tag array write 0
DTB_TAG1 DTB tag array write 1
DTB_PTE0 DTB PTE array write 0
DTB_PTE1 DTB PTE array write 1
DTB_ALTMODE DTB alternate processor mode
DTB_IAP DTB invalidate all process
ASM = 0
DTB_IA DTB invalidate all process
Alpha 21264/EV67 Hardware Reference Manual
Internal Processor Register Power-Up Reset State
Reset State Comments
X
X
X
X
X
X
X
X
X
X
X
Cleared
IC_EN = 3 All other bits are cleared on reset.
X
X
X
X
PCTX[FPE] is set. All other bits are cleared.
X
X
X
X
X
X
Cleared
Cleared
Cleared
Cleared
X
X
X
—
Must be written to in PALcode.
—
—
—
—
Must be written to in PALcode.
—
—
Must be cleared in PALcode.
—
—
Must be cleared in PALcode.
—
—
—
Must be cleared in PALcode.
Must be cleared in PALcode.
Must be cleared in PALcode.
—
—
Must be cleared in PALcode.
—
—
—
—
PALcode must initialize.
—
Must be written to in PALcode.
Initialization and Configuration
7–15