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Bcache Port
When the Cbox CSR BC_BANK_ENABLE[0] is not set, the unused BcAdd_H[23:4]
pins are tied to zero. For example, when configured as a 4MB cache, the 21264/EV67
never changes BcAdd_H[23:22] from logic zero, and when BC_BANK_ENABLE[0]
is asserted, the 21264/EV67 drives the complement of the MSB index on the next
higher BcAdd_H pin.
4.8.4.2 Bcache Control Pins
The Bcache control pins (BcLoad_L, BcDataWr_L, BcDataOE_L, BcTagWr_L,
BcTagOE_L) are controlled using Cbox CSRs BC_BURST_MODE_ENABLE[0] and
BC_PENTIUM_MODE[0].
Table 4–43 shows the four combinations of Bcache control pin behavior obtained using
the two CSRs.
Table 4–43 Programming the Bcache Control Pins
BC_PENTIUM_MODE
0
0
1
1
Table 4–44 lists the combination of control pin assertion for
Table 4–44 Control Pin Assertion for RAM_TYPE A
TYPE_A
BcLoad_L
BcDataOE_L
BcDataWr_L
BcTagOE_L
BcTagWr_L
Table 4–45 lists the combination of control pin assertion for RAM_TYPE B.
Table 4–45 Control Pin Assertion for RAM_TYPE B
TYPE_B
BcLoad_L
BcDataOE_L
BcDataWr_L
BcTagOE_L
BcTagWr_L
Cache and External Interfaces
4–52
BC_BURST_MODE_ENABLE
0
1
0
1
NOP RA0
RA1
RA2
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
H
NOP
RA0
RA1
RA2
H
L
H
H
H
L
L
L
L
H
H
H
H
L
H
H
H
H
H
H
RAM_TYPE
RAM_TYPE A
RAM_TYPE B
Unsupported
Unsupported
RA3
NOP NOP WA0 WA1
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
RA3
NOP
NOP
WA0 WA1 WA2 WA3 NOP
H
H
H
L
L
H
H
L
H
L
L
L
H
H
H
L
H
H
H
L
Alpha 21264/EV67 Hardware Reference Manual
.
RAM_TYPE A
WA2
WA3
NOP
H
H
H
H
L
L
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
L
H
H
H
H
H
H
H
H
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