Compaq 21264 Hardware Reference Manual page 355

Store instructions
Dcache ECC errors with
,
I/O address space 2–29
I/O reference ordering
,
Mbox order traps 2–31
memory address space
memory reference ordering
translation to external interface
,
Store queue 2–13
,
Store-load order trap 2–32
STx_C instructions
in-order processing for
locking mechanism for
Supply voltage signal pins. See I_DC_POWER pin
type
Synchronous static random-access memory. See
SSRAMs
SYS_BPHASE_LD_VECTOR Cbox CSR
,
defined 5–38
SYS_BUS_FORMAT Cbox CSR, defined
SYS_BUS_SIZE Cbox CSR
,
defined 5–34
SYS_CLK_DELAY Cbox CSR, defined
SYS_CLK_LD_VECTOR Cbox CSR
,
defined 5–38
SYS_CLK_RATIO Cbox CSR, defined
SYS_CLKFWD_ENABLE Cbox CSR, defined
5–36
SYS_CPU_CLK_DELAY Cbox CSR
,
defined 5–38
SYS_DDM_FALL_EN Cbox CSR
,
defined 5–36
SYS_DDM_RD_FALL_EN Cbox CSR
SYS_DDM_RD_RISE_EN Cbox CSR
SYS_DDM_RISE_EN Cbox CSR
,
defined 5–36
SYS_DDMF_ENABLE Cbox CSR
,
defined 5–36
SYS_DDMR_ENABLE Cbox CSR
,
defined 5–36
SYS_FDBK_EN Cbox CSR
,
defined 5–38
SYS_FRAME_LD_VECTOR Cbox CSR
4–31
,
defined 5–38
SYS_RCV_MUX_CNT_PRESET Cbox CSR
,
defined 5–36
SYS_RCV_MUX_PRESET Cbox CSR
,
SysAddIn_L signal pins
SysAddInClk_L signal pin
,
SysAddOut_L signal pins
Alpha 21264/EV67 Hardware Reference Manual
,
8–4
,
2–31
,
2–29
,
2–31
,
4–5
,
4–15
,
4–14
,
4–18
,
5–34
,
4–21
,
5–36
,
4–18
,
5–34
,
,
4–18
,
4–18
,
4–19
,
4–18
,
4–19
,
4–19
,
4–18
, ,
4–19
,
4–31
,
4–33
3–5
,
3–5
3–5
SysAddOutClk_L signal pin
SYSBUS_ACK_LIMIT Cbox CSR
,
defined 5–34
SYSBUS_FORMAT Cbox CSR
SYSBUS_MB_ENABLE Cbox CSR
,
defined 5–34
,
operation 2–32
SYSBUS_VIC_LIMIT Cbox CSR
,
defined 5–34
,
SysCheck_L signal pin 3–5
,
SYSCLK 4–31
,
SysData_L signal pin 3–5
SysDataInClk_H signal pin
SysDataInValid_L signal pin
,
rules for 4–34
SysDataOutClk_L signal pin
SysDataOutValid_L signal pin
,
rules for 4–35
,
SysDc commands 4–11
,
system probes, with
SysDc field, system to 21264/EV67 commands
4–29
SYSDC_DELAY Cbox CSR
,
defined 5–38
,
SysFillValid_L signal pin
,
rules for 4–35
System clock ratio configuration
,
System initialization 7–7
System interface clocks, programming
,
System port 4–16
,
SysVref signal pin 3–6
T
,
Tag parity errors 8–2
, ,
TB fill flow 2–34 6–14
,
Tck_H signal pin 3–6
,
Tdi_H signal pin 3–6
,
Tdo_H signal pin 3–6
Temperatures
maximium average per frequency
,
operating 10–1
,
Terminology xix
,
TestStat_H signal pin 3–6
,
purpose for 11–4
with BiST and SROM load
Thermal design characteristics
,
Tms_H signal pin 3–6
,
3–5
,
4–25
,
4–21
,
4–23
,
4–26
,
3–5
,
3–5
,
3–5
,
3–5
4–42
,
,
4–32
3–5
,
7–4
,
4–18
,
10–2
,
7–6
,
10–7
Index–11