Compaq 21264 Hardware Reference Manual page 75

Table 3–3 21264/EV67 Signal Descriptions by Function (Continued)
Signal
BcVref
SysVref Domain
SysAddIn_L[14:0]
SysAddInClk_L
SysAddOut_L[14:0]
SysAddOutClk_L
SysCheck_L[7:0]
SysData_L[63:0]
SysDataInClk_H[7:0]
SysDataInValid_L
SysDataOutClk_L[7:0] O_OD
SysDataOutValid_L
SysFillValid_L
SysVref
Clocks and PLL
ClkIn_H
ClkIn_L
EV6Clk_H
EV6Clk_L
FrameClk_H
FrameClk_L
PLL_VDD
MiscVref Domain
ClkFwdRst_H
DCOK_H
IRQ_H[5:0]
MiscVref
PllBypass_H
Alpha 21264/EV67 Hardware Reference Manual
Type Count Description
I_DC_REF 1 Tag data input reference voltage.
I_DA 15 Time-multiplexed SysAddIn, system-to-21264/EV67.
I_DA 1 Single-ended forwarded clock from system for
SysAddIn_L[14:0] and SysFillValid_L.
O_OD 15 Time-multiplexed SysAddOut, 21264/EV67-to-system.
O_OD 1 Single-ended forwarded-clock.
B_DA_OD 8 Quadword ECC check bits for SysData_L[63:0].
B_DA_OD 64 Data bus for memory and I/O data.
I_DA 8 Single-ended system-generated clocks for clock forwarded
input system data.
I_DA 1 When asserted, marks a valid data cycle for data transfers to
the 21264/EV67.
8 Single-ended 21264/EV67-generated clocks for clock for-
warded output system data.
I_DA 1 When asserted, marks a valid data cycle for data transfers
from the 21264/EV67.
I_DA 1 Validation for fill given in previous SysDC command.
I_DC_REF 1 System interface reference voltage.
I_DA_CLK 2 Differential input signals provided by the system.
O_PP_CLK 2 Provides an external test point to measure phase alignment of
the PLL.
I_DA_CLK 2 A skew-controlled differential 50% duty cycle copy of the
system clock. It is used by the 21264/EV67 as a reference, or
framing, clock.
3.3 V 1 3.3-V dedicated power supply for the 21264/EV67 PLL.
I_DA 1 Systems assert this synchronous signal to wake up a powered-
down 21264/EV67. The ClkFwdRst_H signal is clocked into
a 21264/EV67 register by the captured FrameClk_x signals.
I_DA 1 dc voltage OK. Must be deasserted until dc voltage reaches
proper operating level. After that, DCOK_H is asserted.
I_DA 6 These six interrupt signal lines may be asserted by the system.
I_DC_REF 1 Reference voltage for miscellaneous pins.
I_DA 1 When asserted, this signal will cause the input clocks
(ClkIn_x) to be applied to the 21264/EV67 internal circuits,
instead of the 21264/EV67's global clock (GCLK).
21264/EV67 Signal Names and Functions
Hardware Interface
3–7