A.2.2 Opcodes Reserved for PALcode
Table A–4 lists the 21264/EV67-specific instructions. See Chapter 2 for more
information.
Table A–4 Opcodes Reserved for PALcode
21264/EV67
Mnemonic
Opcode
HW_LD
1B
HW_ST
1F
HW_REI
1E
HW_MFPR
19
HW_MTPR
1D
A.3 IEEE Floating-Point Instructions
Table A–5 lists the hexadecimal value of the 11-bit function code field for the IEEE
floating-point instructions, with and without qualifiers. The opcode for these
instructions is 16
Table A–5 IEEE Floating-Point Instruction Function Codes
Mnemonic
ADDS
ADDT
CMPTEQ
CMPTLT
CMPTLE
CMPTUN
CVTQS
CVTQT
CVTST
CVTTQ
CVTTS
DIVS
DIVT
MULS
MULT
Alpha 21264/EV67 Hardware Reference Manual
Architecture
Mnemonic
Function
PAL1B
Performs Dstream load instructions.
PAL1F
Performs Dstream store instructions.
PAL1E
Returns instruction flow to the program counter (PC) pointed
to by EXC_ADDR internal processor register (IPR).
PAL19
Accesses the Ibox, Mbox, and Dcache IPRs.
PAL1D
Accesses the Ibox, Mbox, and Dcache IPRs.
.
16
None
/C
/M
080
000
040
0A0
020
060
0A5
—
—
0A6
—
—
0A7
—
—
0A4
—
—
0BC
03C
07C
0BE
03E
07E
See
—
—
below
See
—
—
below
0AC
02C
06C
083
003
043
0A3
023
063
082
002
042
0A2
022
062
IEEE Floating-Point Instructions
/D
/U
/UC
0C0
180
100
0E0
1A0
120
—
—
—
—
—
—
—
—
—
—
—
—
0FC
—
—
0FE
—
—
—
—
—
—
—
—
0EC
1AC
12C
0C3
183
103
0E3
1A3
123
0C2
182
102
0E2
1A2
122
Alpha Instruction Set
/UM
/UD
140
1C0
160
1E0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16C
1EC
143
1C3
163
1E3
142
1C2
162
1E2
A–9